From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id Z5hJHSm5jGjwpQEAWB0awg (envelope-from ) for ; Fri, 01 Aug 2025 08:55:05 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZuMdTXtG; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 6185B1E102; Fri, 1 Aug 2025 08:55:05 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-10.1 required=5.0 tests=ARC_SIGNED,ARC_VALID, BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_VALIDITY_CERTIFIED, RCVD_IN_VALIDITY_RPBL,RCVD_IN_VALIDITY_SAFE autolearn=ham autolearn_force=no version=4.0.1 Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 77A5B1E091 for ; Fri, 1 Aug 2025 08:55:04 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1583F3858C78 for ; Fri, 1 Aug 2025 12:55:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1583F3858C78 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZuMdTXtG Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id F1B273858420 for ; Fri, 1 Aug 2025 12:54:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F1B273858420 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F1B273858420 Authentication-Results: server2.sourceware.org; arc=fail smtp.remote-ip=192.198.163.7 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1754052855; cv=fail; b=qA5kokKANv4nYg9JCmcZVjKTyxlV74tYQjGygpshemHY0v83JMI32U78VfawsGpOo5XPHg02ngxEGnUqM+ncdgq/8tgQ9XECA8R/PAYzoWVTrrfUvWuQgfj0SQS3V0uLdso9jal8mMHsgtxIPOV/lWKGlbupU9tINpK/qQH4b1k= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1754052855; c=relaxed/simple; bh=HEnO2jEiDLy8pL71SztwxBpAoTCg+lb6cESXTfrZxvg=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=dlo/VEf06ylTNYx3pl4TRJLEqhuPbvBSOIL1oLoCirI6n63kttn4v+0x47MFeRAYphVzB6Z54G8EHurfj221gHkTURvscJMvfEcvqgl8rA7FeThHQPpofjqLr+ezEwFfHsMVIrJjp5tf+EPIRAU9ciptXkNCv3bGiTC07G9rQr4= ARC-Authentication-Results: i=2; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F1B273858420 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754052855; x=1785588855; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version:content-transfer-encoding; bh=HEnO2jEiDLy8pL71SztwxBpAoTCg+lb6cESXTfrZxvg=; b=ZuMdTXtGLt5dOL8QdLjqVIwzuPnoEIDg04NVtLEvevpRHr5G/A91y29l 10Auzm0sOpS0Tv8FaGPKsw+K9sj8pXBqKmLeC5PwKnze73k+xHSkby0+Y sr0zpXAYsbMulwLOPgyJ/L6oQq15roBA7+TB02FhNjmdB3JtZP/blwrCv Z49xaQUAqcoGMlWXFKluhrS6CY35AYQzSbxBuMBm7+8TOQDq/O4TYpwh5 LS44Q/64CJKaGBQ8eni93RooXlAeioAyyOs4qZuYKl8xU39N7P1UNtTfU QmXdy+RJqm91chXCEDv5DeF9FBOTnziAEaYd6pKlLxCp5c7hKA+AiwgHd A==; X-CSE-ConnectionGUID: ujA/SGk4S3yUWTPz1uMyAg== X-CSE-MsgGUID: VUFPFbPXTRGqZvbogmplkw== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="81852944" X-IronPort-AV: E=Sophos;i="6.17,255,1747724400"; d="scan'208";a="81852944" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2025 05:54:14 -0700 X-CSE-ConnectionGUID: wZ9/Rk9lRxKAm4tgvgBl1Q== X-CSE-MsgGUID: 6HJgvMnlRRSdG9nuwr19UQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,255,1747724400"; d="scan'208";a="187236039" Received: from orsmsx903.amr.corp.intel.com ([10.22.229.25]) by fmviesa002.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2025 05:54:13 -0700 Received: from ORSMSX903.amr.corp.intel.com (10.22.229.25) by ORSMSX903.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Fri, 1 Aug 2025 05:54:13 -0700 Received: from ORSEDG902.ED.cps.intel.com (10.7.248.12) by ORSMSX903.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26 via Frontend Transport; Fri, 1 Aug 2025 05:54:13 -0700 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (40.107.93.60) by edgegateway.intel.com (134.134.137.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 1 Aug 2025 05:54:13 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=o2Pjp8bcuKhUOmjNbvLpJGLqdo4SRwyaR0XaP7WkseOz51fDnZEuMT2uQOVDEcV2e7aDJ6dnxQrjRqUPLf9dePhieaQ6i2yucEAggTa64LL3ilGh1Nh4QTH55NBa76QVxk+NMtmGGTdItl3Xscir1tYFkv3G+yrnP28rYx7F6el31+V1FAtSlMJVNQ7koWBv44maniVKZH9xNF8BHb26CHsqeLRvsVQP5xznOz7e6H1CTOswPqyyijNrZWLQNBfP1YmLEnQ8PkhLIgsjP9onzWQ5XHkWLdmmi9tQyUPmQWFHxj0Oj+e+TD0PTYkNn2Od7UeGEk+IWqVJx1ybMBe7dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=E2p2KA4HDnTwfQp4LoagBgvVe1EDrZUJQobHqO+l/bY=; b=KCInU48lCi3fhhQO0o4hy391ITTDCSxbsXoluQVU5pvM4eQwtvdj0lQOgR1SfV7h+e24MQ4rkYRQrT1fTQh53Ha+ruclXBJ8gjFcma2K52K4t6yV94Jdw3VV2RLhj6BmWu9/qNF+TdIvWj036hxWIj9mlPydv70YnlgdZw37z6PA2x/VToEMd3J7XHHUJy8rxz+KKLDtzI0tv0142mz670wgbEVyu9aaAYBPJQ0cNMxIBdRPMHpQMOF1BV+SNFYd8zr2hSxex/TM80DYGuJ8HNDN6Jhf1VS8OL8AsVvoZye/bufy3y3mKLK6XGr0gAGFpr/gnCnDKTDd2MmvY+LrPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from SN7PR11MB7638.namprd11.prod.outlook.com (2603:10b6:806:34b::22) by DS0PR11MB7442.namprd11.prod.outlook.com (2603:10b6:8:14d::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8964.24; Fri, 1 Aug 2025 12:54:11 +0000 Received: from SN7PR11MB7638.namprd11.prod.outlook.com ([fe80::25b8:16dc:755e:34d1]) by SN7PR11MB7638.namprd11.prod.outlook.com ([fe80::25b8:16dc:755e:34d1%5]) with mapi id 15.20.8964.023; Fri, 1 Aug 2025 12:54:11 +0000 From: "Schimpe, Christina" To: "Schimpe, Christina" , Andrew Burgess , "gdb-patches@sourceware.org" CC: "thiago.bauermann@linaro.org" , "luis.machado@arm.com" Subject: RE: [PATCH v5 06/12] gdb, gdbserver: Add support of Intel shadow stack pointer register. Thread-Topic: [PATCH v5 06/12] gdb, gdbserver: Add support of Intel shadow stack pointer register. Thread-Index: AQHb6Acq3rWeR1UfBECDbgcmq9LBerRC9SqAgAAL4gCACvHMsA== Date: Fri, 1 Aug 2025 12:54:11 +0000 Message-ID: References: <20250628082810.332526-1-christina.schimpe@intel.com> <20250628082810.332526-7-christina.schimpe@intel.com> <87cy9oe8pc.fsf@redhat.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN7PR11MB7638:EE_|DS0PR11MB7442:EE_ x-ms-office365-filtering-correlation-id: 9fa8feca-324b-4f99-839e-08ddd0fa82e6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|366016|1800799024|38070700018; x-microsoft-antispam-message-info: =?us-ascii?Q?ub78CXqU2sMYh5krvvrga+irklTxezQqxg5IMXOCmLo9SN4q525KVaRvh0i9?= =?us-ascii?Q?e9AtL3cLcDf3wNOJZD+ZGJC1VRQuqLH5E6slt8UjslmZNByigPFp9ZC6HBI6?= =?us-ascii?Q?qsHmRTqfJynrIkj+hayQzOkgyQVQDZ34gNMDtGY47ENmTi7XJfT2ov7qtFQt?= =?us-ascii?Q?Che/b5/42Pp8dYrOXkDZzjkwvOxwo3KhEzV/vTwaecds/tV9eG/9S6HPErCu?= =?us-ascii?Q?05ODSyJX9bX3Lk9U4BWvcbOKRsLe69DFLAQlpQayglWgiQBcicEZjbCftaho?= =?us-ascii?Q?r7urMODAvNr4avMwRW3+fEhevCtWnDhrT3/jVNeaWNp6CNuaNqGuwBBOShwV?= =?us-ascii?Q?ptf4UAeAE1LEG5cK69qKOr3mqstq/VPhPl+9Z7jqgOHic6QO3Fkr4H0RtSfJ?= =?us-ascii?Q?T66hJzz/hD1QVJeX0KMN9HF3S9c2iqhmIiNjA9fOgOa6Mrs9oXWbb15w5T2R?= =?us-ascii?Q?GawI4A3HbhU9tY3P9qo6bKbCVqPYs3V0NtTpls5EBiNVk7pshndy9s50Qjlx?= =?us-ascii?Q?R5qQNBFKqBjSK/4hQFXZ1FQu/sgWuNppgHzFojTE+7iOsehhPKk3/BZcsmFw?= =?us-ascii?Q?Euf6sqjc37oMqercb7UkSYdOpN1+T4ER6WryTTviJIM161SCuzCMdd6yXz6v?= =?us-ascii?Q?iBUTo5TgBiVLqvNJ9QXxWOoEOpxVZGjJ08bcpNrcfIrlexeiOtdxtORsEo6p?= =?us-ascii?Q?CYmIlJJQAYQmphruE8usphfWZHE+8xZQSa2gmgUSi0ZUlZtYIhxrH/30zPMX?= =?us-ascii?Q?hitGnuoB29Qyj0vC63ZtZK/Ok6MMHwuFJysUJyPEd4otL2SvhE5RjN2iSvi6?= =?us-ascii?Q?/nj9xASDbpkTls59IIJ+XouFeyFi5u+anr9mDqV/cC7mXYMd+X7PEbjEYL/4?= =?us-ascii?Q?wv/4X3a9yEyHaOgQmYKZuMaEI7WaP+PFIDnmsYK273TNd/Tssg0ynzW80NKU?= =?us-ascii?Q?UqoYuqgODyasOcCH4EqgIvglU5m7Y6hz2fS5YrYmV2gDxM1ctimrPNwXaJYu?= =?us-ascii?Q?JjwyUwnkmeK7XIKXSsKrt8vNwggammqoWRWJcKwDXHekcM2Xa0faOL0oDe6R?= =?us-ascii?Q?Hf8eLxUYvDszZVceSjHx85iyim2amghqd51sdSxyv/3ZwDDPZGRS1ff1DTg6?= =?us-ascii?Q?8kTRfdGdZTXPJGtbHOvnKt3XYoI89BDdl+PhqerhM251Wz8hllFYEJjDClxl?= =?us-ascii?Q?hGtlP59F0t6tPvurZaiX7MbeAQFzSLX57n5u4yv+iPrk4sGKThYXmcv/AHL0?= =?us-ascii?Q?kM0n4miQh3tMDRtzk68vVXhQa+HwgCNWMzm5ejB1qlppbaQqBsEtRPxM+n8Y?= =?us-ascii?Q?g9wELPlY6fR+VLl00tu/fRBNwqldronYgKs6NbvV7Z4ttRqH6E1F8nL4tvBJ?= =?us-ascii?Q?A44yKmId6siwBHJw+jIX36OMBUDapiJnpTxBQh2luIRuBiz9CVtyLbz0HYM1?= =?us-ascii?Q?nfnrtCvTqpteeTOqJRUHAdGLCvK8ooZq?= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN7PR11MB7638.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(366016)(1800799024)(38070700018); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?vg19YldXLfnEn9baqbNBosfRDKHXtERbeWOEeI5BQ1zwdSNeSyCMpfQJ2Z2R?= =?us-ascii?Q?9W032DwyJPkC//I8OtANdXKPNP9bnCv7FmpCaF6hZ38X3hLBtETAXZF9lCSM?= =?us-ascii?Q?I1mufQ4YCvyBwt+oe7SnFiDAoNIBjn9da0nfaUKyXnGiPZSCBsJ+ruW4phHB?= =?us-ascii?Q?3jM3YRR64aaEKJaGoC3ZtkLzcMy0A3dUWkobBqN0oJRmpsQqZkIzTtvE7iY/?= =?us-ascii?Q?rwWEHzaALZmuT8ODLsufVPTCACzKqwy9tCP+7OerxT7MGyJI0kikE1Xb19/J?= =?us-ascii?Q?KMOkJ42/u/SCEoKg8gvFfcNM+e6gDwVhgqTYICPANF0m3hGLzrpbEcY7B7Pz?= =?us-ascii?Q?6miSLJE8vej1NR3aRLBMjG3Q79zIVVoLH1As73psABo1WkBd3GfLhpwoAqX5?= =?us-ascii?Q?mEVT5ro3cUI5pQyL7e+yojkyAFb49BEAG+EioZ/aZPKaOH20UOPDDC4OLw1F?= =?us-ascii?Q?Wu5P9vmb7bnWUZJcnwrAN3L+8q0Beko4KpsjP1GKBuaBVPwZwNg45Rjccrb/?= =?us-ascii?Q?JjrMALidHrDe5iEljtdikPuDvKPUFALlPrJY5p8fI1CI+o1D0sZtGx0F1U1e?= =?us-ascii?Q?Vs/wh1OQKHqyNJkCv0zJEQRlhG9VDTX9gd+Unc0FCDrsbmkfdXGHJeaA8F+e?= =?us-ascii?Q?5U3+U1L2JtGPT9yUAXMd2XulugvzQlpcrif8bl53Y9PR9c5qqcx14KFoOxjU?= =?us-ascii?Q?4qisMhmONxZwf8V/+mME1k45POhuNKSBl1H3mm5y7FCPCuYDiW95Hzb2Cnkp?= =?us-ascii?Q?WBliNZi1CRiE+IbQM6RgcGmFUb5QyOHmaNiDmjkTcKOcrLMBdFucgDscSo4l?= =?us-ascii?Q?OUwyHdWZIvWpfGs6ivq4RTWvSZItCqR9XjAcTpl6Gswg5ZDtkXQ3aLDAMoQK?= =?us-ascii?Q?AA5RR+6OTcJj4aIIcYFco0rDXRYZ871hklNiRHiBMJ03lJb7SY4cuP2xEz5j?= =?us-ascii?Q?/r/VYRB4F5tKPdQ44EPQ5b9aAkdLMPU9ve29PhzwmU66xyo6pp3nRjsWxXWh?= =?us-ascii?Q?kRSkPIsT5c7pqxOot8/vpOhChpKB/41UlgpXH6tpYVNr8oupOrDYCSg5e5cp?= =?us-ascii?Q?U3XqJu3tQT6cDDSd7OfE4UqxPuV7ReVClVAACj+6iEuDQEnRmGVF5myd6h4P?= =?us-ascii?Q?i75v3FBXg7pw8upMELtDfSWo61hsHJMIlQ+oZO7mTtdGq/w5pYDjjluRoEKw?= =?us-ascii?Q?nqeKlLTonQMKhaVezhjxkiMIuO2wgEHd2EbHq02SOMCgZ54fxyah34R2JeWS?= =?us-ascii?Q?AF0VGbvDydfj0dp2YHyXg8/HtF29GVcoVwGyjArtl/ypIejfhrnJbCQe9RUH?= =?us-ascii?Q?tijcCOPe7XsgF4k7CV6XmgscRs1KmfsmRKy2pCdXuFDsyQoD5+1sbC51y+mU?= =?us-ascii?Q?bLZfwSnCX+YvTlrCYL6KA0ZDTW28WCw3Bd8waN8t37e3d041JPRfUsnkzhWX?= =?us-ascii?Q?SfL1Xii+aCA6fVaka5oN6abSv1O93eg/vlmkZrmu5/Bdr/cTLcMkj9v4hoBZ?= =?us-ascii?Q?pRGs8huEGaun0dfEY8kUBwaOBEZpsUtrAx6u/jmcbYCKGMt0vcmRZlxQ5VEL?= =?us-ascii?Q?Tcbz5NaT5wSiz6gzwggge0+NWZD3KHip9pPo2w5cRH2xOJqx8nASIxx9UxTZ?= =?us-ascii?Q?Eg=3D=3D?= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN7PR11MB7638.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9fa8feca-324b-4f99-839e-08ddd0fa82e6 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 12:54:11.2389 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Xg4RCaKmDR4eh1kyU2Hnl5Ik9WO2/XkgIolW43/AVOs9Buhe7hqaB3XhsXcD9Av5YA32uozxHYT7wscY3p+aHzTWYI2ZexJUSHgAHiGvdRQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7442 X-OriginatorOrg: intel.com Content-Transfer-Encoding: quoted-printable X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Hi Andrew, > -----Original Message----- > From: Schimpe, Christina > Sent: Friday, July 25, 2025 5:04 PM > To: Andrew Burgess ; gdb-patches@sourceware.org > Cc: thiago.bauermann@linaro.org; luis.machado@arm.com > Subject: RE: [PATCH v5 06/12] gdb, gdbserver: Add support of Intel shadow > stack pointer register. > = > Hi Andrew, > = > Thanks a lot for the review! I have some questions for your feedback, ple= ase > find my comments below. > = > > -----Original Message----- > > From: Andrew Burgess > > Sent: Friday, July 25, 2025 2:50 PM > > To: Schimpe, Christina ; gdb- > > patches@sourceware.org > > Cc: thiago.bauermann@linaro.org; luis.machado@arm.com > > Subject: Re: [PATCH v5 06/12] gdb, gdbserver: Add support of Intel > > shadow stack pointer register. > > > > Christina Schimpe writes: > > > > > This patch adds the user mode register PL3_SSP which is part of the > > > Intel(R) Control-Flow Enforcement Technology (CET) feature for > > > support of shadow stack. > > > For now, only native and remote debugging support for shadow stack > > > userspace on amd64 linux are covered by this patch including 64 bit > > > and > > > x32 support. 32 bit support is not covered due to missing Linux > > > kernel support. > > > > > > This patch requires fixing the test > > > gdb.base/inline-frame-cycle-unwind > > > which is failing in case the shadow stack pointer is unavailable. > > > Such a state is possible if shadow stack is disabled for the current > > > thread but supported by HW. > > > > > > This test uses the Python unwinder inline-frame-cycle-unwind.py > > > which fakes the cyclic stack cycle by reading the pending frame's > > > registers and adding them to the unwinder: > > > > > > ~~~ > > > for reg in pending_frame.architecture().registers("general"): > > > val =3D pending_frame.read_register(reg) > > > unwinder.add_saved_register(reg, val) > > > return unwinder > > > ~~~ > > > > > > However, in case the python unwinder is used we add a register > > > (pl3_ssp) that is unavailable. This leads to a NOT_AVAILABLE_ERROR > > > caught in gdb/frame-unwind.c:frame_unwind_try_unwinder and it is > > > continued with standard unwinders. This destroys the faked cyclic > > > behavior and the stack is further unwinded after frame 5. > > > > > > In the working scenario an error should be triggered: > > > ~~~ > > > bt > > > 0 inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:49^M > > > 1 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M > > > 2 0x000055555555516e in inline_func () at > > > /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M > > > 3 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M > > > 4 0x000055555555516e in inline_func () at > > > /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M > > > 5 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M > > > Backtrace stopped: previous frame identical to this frame (corrupt > > > stack?) > > > (gdb) PASS: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 5: > > > backtrace when the unwind is broken at frame 5 ~~~ > > > > > > To fix the Python unwinder, we simply skip the unavailable registers. > > > > > > Reviewed-by: Thiago Jung Bauermann > > > Reviewed-By: Eli Zaretskii > > > Reviewed-By: Luis Machado > > > --- > > > gdb/NEWS | 3 + > > > gdb/amd64-linux-nat.c | 17 +++++ > > > gdb/amd64-linux-tdep.c | 1 + > > > gdb/amd64-tdep.c | 6 +- > > > gdb/amd64-tdep.h | 1 + > > > gdb/arch/amd64.c | 10 +++ > > > gdb/arch/i386.c | 4 ++ > > > gdb/arch/x86-linux-tdesc-features.c | 1 + > > > gdb/doc/gdb.texinfo | 4 ++ > > > gdb/features/Makefile | 2 + > > > gdb/features/i386/32bit-ssp.c | 14 ++++ > > > gdb/features/i386/32bit-ssp.xml | 11 +++ > > > gdb/features/i386/64bit-ssp.c | 14 ++++ > > > gdb/features/i386/64bit-ssp.xml | 11 +++ > > > gdb/i386-tdep.c | 22 +++++- > > > gdb/i386-tdep.h | 4 ++ > > > gdb/nat/x86-linux-tdesc.c | 2 + > > > gdb/nat/x86-linux.c | 57 +++++++++++++++ > > > gdb/nat/x86-linux.h | 4 ++ > > > gdb/testsuite/gdb.arch/amd64-shadow-stack.c | 22 ++++++ > > > gdb/testsuite/gdb.arch/amd64-ssp.exp | 50 +++++++++++++ > > > .../gdb.base/inline-frame-cycle-unwind.py | 4 ++ > > > gdb/testsuite/lib/gdb.exp | 70 +++++++++++++++++= ++ > > > gdb/x86-linux-nat.c | 49 +++++++++++-- > > > gdb/x86-linux-nat.h | 11 +++ > > > gdb/x86-tdep.c | 21 ++++++ > > > gdb/x86-tdep.h | 9 +++ > > > gdbserver/linux-x86-low.cc | 28 +++++++- > > > gdbsupport/x86-xstate.h | 5 +- > > > 29 files changed, 447 insertions(+), 10 deletions(-) create mode > > > 100644 gdb/features/i386/32bit-ssp.c create mode 100644 > > > gdb/features/i386/32bit-ssp.xml create mode 100644 > > > gdb/features/i386/64bit-ssp.c create mode 100644 > > > gdb/features/i386/64bit-ssp.xml create mode 100644 > > > gdb/testsuite/gdb.arch/amd64-shadow-stack.c > > > create mode 100644 gdb/testsuite/gdb.arch/amd64-ssp.exp > > > > > > > > > > diff --git a/gdb/amd64-linux-nat.c b/gdb/amd64-linux-nat.c index > > > dbb9b3223cb..4df99ccca54 100644 > > > --- a/gdb/amd64-linux-nat.c > > > +++ b/gdb/amd64-linux-nat.c > > > @@ -32,6 +32,7 @@ > > > #include "amd64-tdep.h" > > > #include "amd64-linux-tdep.h" > > > #include "i386-linux-tdep.h" > > > +#include "x86-tdep.h" > > > #include "gdbsupport/x86-xstate.h" > > > > > > #include "x86-linux-nat.h" > > > @@ -237,6 +238,14 @@ amd64_linux_nat_target::fetch_registers > (struct > > > regcache *regcache, int regnum) > > > > > > if (have_ptrace_getregset =3D=3D TRIBOOL_TRUE) > > > { > > > + if ((regnum =3D=3D -1 && tdep->ssp_regnum > 0) > > > + || (regnum !=3D -1 && regnum =3D=3D tdep->ssp_regnum)) > > > > It's really nit-picking, but I don't think the '>' here check is > > correct. You're checking that tdep->ssp_regnum has been assigned a > > value, right? And it's default value is -1, so, shouldn't the check re= ally be > '>=3D 0' or '!=3D -1' maybe? > > > > The same pattern is repeated below in ::store_registers. > > > > Ahh, reading further on, I see that (not just you), but all the > > *_regnum fields in i386_gdbarch_tdep start set to 0 (which is a valid > > register number), but are set to -1 if the feature is not found. > > Maybe I'm missing something incredibly clever about this ... but I > > suspect this code is just showing its age a little. I still think the = validity > check should be against -1. > = > Yes I agree, it seems to me that there is something inconsistent in GDB. > = > The current default value is 0, we set all regnums to 0 initially in gdb/= i386- > tdep.h And we set it to -1 to indicate the absence of that specific regis= ter. > = > But on the other hand the enums (enum amd64_regnum/enum > i386_regnum) defining the register numbers start at 0. > = > So that seems to be a separate issue one could consider to fix. > Maybe the default should be simply -1, instead of 0 ? > = > But for my specific patch here the best would be to compare against again= st > -1, I agree and will fix. I created this patch to address the regnum defaults as suggested above: https://sourceware.org/pipermail/gdb-patches/2025-August/219649.html Kind Regards, Christina Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928