From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15368 invoked by alias); 12 Jun 2007 18:14:42 -0000 Received: (qmail 15356 invoked by uid 22791); 12 Jun 2007 18:14:41 -0000 X-Spam-Check-By: sourceware.org Received: from pollux.ds.pg.gda.pl (HELO pollux.ds.pg.gda.pl) (153.19.208.7) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 12 Jun 2007 18:14:35 +0000 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 1F610E1CEA; Tue, 12 Jun 2007 20:14:19 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8JzrlNgLtx1e; Tue, 12 Jun 2007 20:14:18 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id C85D0E1C67; Tue, 12 Jun 2007 20:14:18 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.8) with ESMTP id l5CIEXf0003475; Tue, 12 Jun 2007 20:14:34 +0200 Date: Tue, 12 Jun 2007 18:14:00 -0000 From: "Maciej W. Rozycki" To: Daniel Jacobowitz cc: gdb-patches@sourceware.org Subject: Re: [rfc] Target-described register support for MIPS In-Reply-To: <20070521133939.GA8161@caradoc.them.org> Message-ID: References: <20070521133939.GA8161@caradoc.them.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Status: Clean X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-06/txt/msg00204.txt.bz2 On Mon, 21 May 2007, Daniel Jacobowitz wrote: > Maciej, I copied you in case you see anything obviously wrong with my > choices of required registers, et cetera. You may not be familiar > with the protocol extensions and so forth I've added for target > descriptions - it's been my pet project for the last year or two - but > this is something that I hope would be very useful for MIPS. Could > you look it over? Additional information about the feature is already > in the manual; this is just the MIPS-specific support. Sorry about the delay -- my time constraints are very tight these days. Here are some comments, but I have only had a brief look over your changes and certainly not even attempted to try them at the run time. > +/* Aliases for o32 and most other ABIs. */ > +const struct register_alias mips_o32_aliases[] = { > + { "ta0", 12 }, > + { "ta1", 13 }, > + { "ta2", 14 }, > + { "ta3", 15 } > +}; Hmm, these look wrong -- no "ta" registers have been defined for old ABIs. > + /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS > + backend is not prepared for that, though. */ I do certainly have some patches covering this area -- please check with me before commencing any related work. There are quite a lot of FPU configurations to handle too, including MIPS32r2 processors with 64-bit FPU and MIPS16 code using hard float. > Index: gdb/features/mips64-cp0.xml > =================================================================== > --- /dev/null 1970-01-01 00:00:00.000000000 +0000 > +++ gdb/features/mips64-cp0.xml 2007-05-18 12:01:07.000000000 -0400 > @@ -0,0 +1,13 @@ > + > + > + > + > + > + > + > + > + Hmm, "status" and "cause" are generally 32-bit -- for the MIPS64 architecture dmfc0/dmtc0 on such registers are defined as yielding unpredictable results (and I think at least one implementer did take this seriously), so they should be accessed as 32-bit registers. For legacy chips the results may vary too. The cause register is 64-bit for the R8000 IIRC, but whether it matters should probably be verified by an IRIX user. These are just minor nits. Overall I like the change, though to cover all the optional subsets of cp0 that MIPS32 and MIPS64 specs define quite a lot of DTDs will have to be created. Maciej