From mboxrd@z Thu Jan 1 00:00:00 1970 From: Don Howard To: Eli Zaretskii Cc: , Subject: Re: [RFA] mips: Fix "info registers" output Date: Thu, 21 Jun 2001 14:22:00 -0000 Message-id: References: <1438-Thu21Jun2001215717+0300-eliz@is.elta.co.il> X-SW-Source: 2001-06/msg00373.html I submitted a patch for this problem a while ago. Here is an explaination of the problem as I understood it: Background: MIPS1 & 2 fp registers are 32 bits wide. To support 64bit operations, these early MIPS cpus treat fp register pairs (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp registers and offer a compatibility mode that emulates the MIPS2 fp model. When operating in MIPS2 fp compat mode, later cpu's split double precision floats into two 32-bit chunks and store them in consecutive fp regs. To display 64-bit floats stored in this fashion, we have to combine 32 bits from f0 and 32 bits from f1. Throw in user-configurable endianness and you have a real mess. I'll repost my patch shortly. -- -Don dhoward@redhat.com gdb engineering