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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PR3PR09MB4361.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24860a73-29a7-4353-55fd-08dd187312bf X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Dec 2024 17:01:07.0985 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3o4JoKIgHQcyeh/QMpAqocal1fE/yjfRhitvxtqyvw36zO1h8o7JHtXUpM8hkrUMxPBhsFj32OrDaA/IB34Ho8rUjoNvLTJQ9OHU6cxkjls= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR09MB6859 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Introduce new instruction encodings from Release 6 of the MIPS=0A= architecture [1]. Support breakpoints and single stepping with=0A= compact branches, forbidden slots, new branch instruction and=0A= new atomic load-store instruction encodings.=0A= =0A= Changes from v6: Apply suggestions provided by Kevin Buettner.=0A= =0A= [1] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64=0A= Instruction Set Reference Manual", Document Number: MD00087,=0A= Revision 6.06, December 15, 2016, Section 3 "The MIPS64=0A= Instruction Set", pp. 42-530=0A= https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS= 64BIS-AFP-6.06.pdf=0A= 2024-05-15=0A= Andrew Bennett =0A= Matthew Fortune =0A= Faraz Shahbazker =0A= =0A= ChangeLog:=0A= =0A= gdb/mips-tdep.c=0A= =0A= New functions:=0A= (is_mipsr6_isa)=0A= (mips32_relative_offset21)=0A= (mips32_relative_offset26)=0A= (is_add32bit_overflow)=0A= (is_add64bit_overflow)=0A= (mips32_blez_pc)=0A= (mips32_instruction_is_compact_branch)=0A= (mips32_insn_at_pc_has_forbidden_slot)=0A= (is_ll_insn)=0A= (is_sc_insn)=0A= =0A= Modified functions:=0A= (mips32_next_pc): Handle r6 compact and fpu coprocessor branches.=0A= Move handling of BLEZ, BGTZ opcode into=0A= (mips32_scan_prologue): Ignore pre-r6 addi encoding on r6.=0A= Stop at compact branch also.=0A= (mips_deal_with_atomic_sequence): Use is_ll_insn/is_sc_insn.=0A= Handle compact branches.=0A= (mips_about_to_return): Handle jrc and macro jr.=0A= (mips32_stack_frame_destroyed_p): Likewise.=0A= (mips32_instruction_has_delay_slot): Don't handle JALX on r6.=0A= Handle compact branches and=0A= coprocessor branches.=0A= (mips_adjust_breakpoint_address): Skip forbidden slot for=0A= compact branches.=0A= =0A= gdb/testsuite/gdb.arch/mips-64-r6.c and=0A= gdb/testsuite/gdb.arch/mips-64-r6.exp: tests for the patch.=0A= ---=0A= gdb/mips-tdep.c | 657 +++++++++++++++---=0A= gdb/testsuite/gdb.arch/mips-64-r6.c | 918 ++++++++++++++++++++++++++=0A= gdb/testsuite/gdb.arch/mips-64-r6.exp | 76 +++=0A= 3 files changed, 1556 insertions(+), 95 deletions(-)=0A= create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.c=0A= create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.exp=0A= =0A= diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c=0A= index c00efbd02ad..8d3be54f084 100644=0A= --- a/gdb/mips-tdep.c=0A= +++ b/gdb/mips-tdep.c=0A= @@ -76,6 +76,10 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdba= rch *gdbarch,=0A= static void mips_print_float_info (struct gdbarch *, struct ui_file *,=0A= const frame_info_ptr &, const char *);=0A= =0A= +static void=0A= +mips_read_fp_register_single (const frame_info_ptr &frame, int regno,=0A= + gdb_byte *rare_buffer);=0A= +=0A= /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */=0A= /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */= =0A= #define ST0_FR (1 << 26)=0A= @@ -325,6 +329,17 @@ mips_abi_regsize (struct gdbarch *gdbarch)=0A= }=0A= }=0A= =0A= +/* Return true if the gdbarch is based on MIPS Release 6. */=0A= +=0A= +static bool=0A= +is_mipsr6_isa (struct gdbarch *gdbarch)=0A= +{=0A= + const struct bfd_arch_info *info =3D gdbarch_bfd_arch_info (gdbarch);=0A= +=0A= + return (info->mach =3D=3D bfd_mach_mipsisa32r6=0A= + || info->mach =3D=3D bfd_mach_mipsisa64r6);=0A= +}=0A= +=0A= /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here=0A= are some functions to handle addresses associated with compressed=0A= code including but not limited to testing, setting, or clearing=0A= @@ -657,7 +672,7 @@ mips_register_name (struct gdbarch *gdbarch, int regno)= =0A= =0A= enum mips_abi abi =3D mips_abi (gdbarch);=0A= =0A= - /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, = =0A= + /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,= =0A= but then don't make the raw register names visible. This (upper)=0A= range of user visible register numbers are the pseudo-registers.=0A= =0A= @@ -1002,7 +1017,7 @@ mips_value_to_register (const frame_info_ptr &frame, = int regnum,=0A= size_t len =3D type->length ();=0A= frame_info_ptr next_frame =3D get_next_frame_sentinel_okay (frame);= =0A= =0A= - /* Sign extend values, irrespective of type, that are stored to =0A= + /* Sign extend values, irrespective of type, that are stored to=0A= a 64-bit general purpose register. (32-bit unsigned values=0A= are stored as signed quantities within a 64-bit register.=0A= When performing an operation, in compiled code, that combines=0A= @@ -1496,6 +1511,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= return extract_unsigned_integer (buf, instlen, byte_order);=0A= }=0A= =0A= +=0A= /* These are the fields of 32 bit mips instructions. */=0A= #define mips32_op(x) (x >> 26)=0A= #define itype_op(x) (x >> 26)=0A= @@ -1538,6 +1554,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch,=0A= #define b0s11_op(x) ((x) & 0x7ff)=0A= #define b0s12_imm(x) ((x) & 0xfff)=0A= #define b0s16_imm(x) ((x) & 0xffff)=0A= +#define b0s21_imm(x) ((x) & 0x1fffff)=0A= #define b0s26_imm(x) ((x) & 0x3ffffff)=0A= #define b6s10_ext(x) (((x) >> 6) & 0x3ff)=0A= #define b11s5_reg(x) (((x) >> 11) & 0x1f)=0A= @@ -1574,6 +1591,24 @@ mips32_relative_offset (ULONGEST inst)=0A= return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;=0A= }=0A= =0A= +/* Calculates pc-relative offset from lower 21 bits of instruction.=0A= + Used by BEQZC, BNEZC. */=0A= +=0A= +static LONGEST=0A= +mips32_relative_offset21 (ULONGEST insn)=0A= +{=0A= + return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2;=0A= +}=0A= +=0A= +/* Calculates pc-relative offset from lower 26 bits of an instruction.=0A= + Used by BC, BALC. */=0A= +=0A= +static LONGEST=0A= +mips32_relative_offset26 (ULONGEST insn)=0A= +{=0A= + return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2;=0A= +}=0A= +=0A= /* Determine the address of the next instruction executed after the INST= =0A= floating condition branch instruction at PC. COUNT specifies the=0A= number of the floating condition bits tested by the branch. */=0A= @@ -1632,6 +1667,82 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)= =0A= return 0;=0A= }=0A= =0A= +/* Detects whether overflow occurs when adding two 32-bit integers. */=0A= +=0A= +static int=0A= +is_add32bit_overflow (int32_t a, int32_t b)=0A= +{=0A= + int32_t r =3D (uint32_t) a + (uint32_t) b;=0A= + return (a < 0 && b < 0 && r >=3D 0) || (a >=3D 0 && b >=3D 0 && r < 0);= =0A= +}=0A= +=0A= +/* Helper function for BOVC/BNVC instructions which are introduced in=0A= + MIPS Release 6.=0A= +=0A= + BOVC performs a signed 32-bit addition of two registers. BOVC discards = the=0A= + sum, but detects signed 32-bit integer overflow of the sum (and the inp= uts,=0A= + in MIPS64), and branches if such overflow is detected.=0A= +=0A= + BNVC does the opposite, i.e. branches if such overflow is not detected.= */=0A= +=0A= +static int=0A= +is_add64bit_overflow (int64_t a, int64_t b)=0A= +{=0A= + if (a !=3D (int32_t)a)=0A= + return 1;=0A= + if (b !=3D (int32_t)b)=0A= + return 1;=0A= + return is_add32bit_overflow ((int32_t)a, (int32_t)b);=0A= +}=0A= +=0A= +/* Calculate address of next instruction after BLEZ. */=0A= +=0A= +static CORE_ADDR=0A= +mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache,=0A= + ULONGEST inst, CORE_ADDR pc, int invert)=0A= +{=0A= + int rs =3D itype_rs (inst);=0A= + int rt =3D itype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + ULONGEST uval_rs =3D regcache_raw_get_unsigned (regcache, rs);=0A= + ULONGEST uval_rt =3D regcache_raw_get_unsigned (regcache, rt);=0A= + int taken =3D 0;=0A= + int delay_slot_size =3D 4;=0A= +=0A= + /* BLEZ, BLEZL, BGTZ, BGTZL */=0A= + if (rt =3D=3D 0)=0A= + taken =3D (val_rs <=3D 0);=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + /* BGEZALC, BLTZALC */=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + /* BGEUC, BLTUC */=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (uval_rs >=3D uval_rt);=0A= +=0A= + /* Step through the forbidden slot to avoid repeated exceptions we d= o=0A= + not currently have access to the BD bit when hitting a breakpoint= =0A= + and therefore cannot tell if the breakpoint hit on the branch or t= he=0A= + forbidden slot. */=0A= + /* delay_slot_size =3D 0; */=0A= + }=0A= +=0A= + if (invert)=0A= + taken =3D !taken;=0A= +=0A= + /* Calculate branch target. */=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst);=0A= + else=0A= + pc +=3D delay_slot_size;=0A= +=0A= + return pc;=0A= +}=0A= =0A= /* Determine where to set a single step breakpoint while considering=0A= branch prediction. */=0A= @@ -1642,58 +1753,66 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= struct gdbarch *gdbarch =3D regcache->arch ();=0A= unsigned long inst;=0A= int op;=0A= + int mips64bitreg =3D 0;=0A= +=0A= + if (mips_isa_regsize (gdbarch) =3D=3D 8)=0A= + mips64bitreg =3D 1;=0A= +=0A= inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= op =3D itype_op (inst);=0A= - if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch=0A= - instruction. */=0A= + if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch instruc= tion. */=0A= {=0A= - if (op >> 2 =3D=3D 5)=0A= - /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= - {=0A= - switch (op & 0x03)=0A= - {=0A= - case 0: /* BEQL */=0A= - goto equal_branch;=0A= - case 1: /* BNEL */=0A= - goto neq_branch;=0A= - case 2: /* BLEZL */=0A= - goto less_branch;=0A= - case 3: /* BGTZL */=0A= - goto greater_branch;=0A= - default:=0A= - pc +=3D 4;=0A= - }=0A= - }=0A= + if (op >> 2 =3D=3D 5 && ((op & 0x02) =3D=3D 0 || itype_rt (inst) =3D= =3D 0))=0A= + /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= + {=0A= + switch (op & 0x03)=0A= + {=0A= + case 0: /* BEQL */=0A= + goto equal_branch;=0A= + case 1: /* BNEL */=0A= + goto neq_branch;=0A= + case 2: /* BLEZL */=0A= + goto lez_branch;=0A= + case 3: /* BGTZL */=0A= + goto greater_branch;=0A= + default:=0A= + pc +=3D 4;=0A= + }=0A= + }=0A= else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 8)=0A= - /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= - pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9=0A= + /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= + pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 9=0A= && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */=0A= pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);=0A= - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10=0A= - && (itype_rt (inst) & 2) =3D=3D 0)=0A= + else if (!is_mipsr6_isa (gdbarch)=0A= + && op =3D=3D 17=0A= + && itype_rs (inst) =3D=3D 10=0A= + && (itype_rt (inst) & 2) =3D=3D 0)=0A= /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */=0A= - pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);=0A= - else if (op =3D=3D 29)=0A= - /* JALX: 011101 */=0A= - /* The new PC will be alternate mode. */=0A= - {=0A= - unsigned long reg;=0A= + pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);=0A= + else if (!is_mipsr6_isa (gdbarch) && op =3D=3D 29)=0A= + /* JALX: 011101 */=0A= + /* The new PC will be alternate mode. */=0A= + {=0A= + unsigned long reg;=0A= =0A= - reg =3D jtype_target (inst) << 2;=0A= - /* Add 1 to indicate 16-bit mode -- invert ISA mode. */=0A= - pc =3D ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;=0A= + reg =3D jtype_target (inst) << 2;=0A= + /* Add 1 to indicate 16-bit mode -- invert ISA mode. */=0A= + pc =3D ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;=0A= }=0A= else if (is_octeon_bbit_op (op, gdbarch))=0A= - {=0A= - int bit, branch_if;=0A= + {=0A= + int bit, branch_if;=0A= =0A= - branch_if =3D op =3D=3D 58 || op =3D=3D 62;=0A= - bit =3D itype_rt (inst);=0A= + branch_if =3D op =3D=3D 58 || op =3D=3D 62;=0A= + bit =3D itype_rt (inst);=0A= =0A= - /* Take into account the *32 instructions. */=0A= - if (op =3D=3D 54 || op =3D=3D 62)=0A= + /* Take into account the *32 instructions. */=0A= + if (op =3D=3D 54 || op =3D=3D 62)=0A= bit +=3D 32;=0A= =0A= if (((regcache_raw_get_signed (regcache,=0A= @@ -1703,7 +1822,128 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8; /* After the delay slot. */=0A= }=0A= -=0A= + else if (is_mipsr6_isa (gdbarch))=0A= + {=0A= + /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 8 || op =3D=3D 24)=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + int taken =3D 0;=0A= + /* BOVC (BNVC) */=0A= + if (rs >=3D rt)=0A= + {=0A= + if (mips64bitreg =3D=3D 1)=0A= + taken =3D is_add64bit_overflow (val_rs, val_rt);=0A= + else=0A= + taken =3D is_add32bit_overflow (val_rs, val_rt);=0A= + }=0A= + /* BEQZALC (BNEZALC) */=0A= + else if (rs < rt && rs =3D=3D 0)=0A= + taken =3D (val_rt =3D=3D 0);=0A= + /* BEQC (BNEC) */=0A= + else=0A= + taken =3D (val_rs =3D=3D val_rt);=0A= +=0A= + /* BNVC, BNEZALC, BNEC */=0A= + if (op =3D=3D 24)=0A= + taken =3D !taken;=0A= +=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated except= ions=0A= + we do not currently have access to the BD bit when hitti= ng a=0A= + breakpoint and therefore cannot tell if the breakpoint= =0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + /* BC1EQZ, BC1NEZ */=0A= + else if (op =3D=3D 17 && (itype_rs (inst) =3D=3D 9 || itype_rs (i= nst) =3D=3D 13))=0A= + {=0A= + gdb_byte status;=0A= + gdb_byte true_val =3D 0;=0A= + unsigned int fp =3D (gdbarch_num_regs (gdbarch)=0A= + + mips_regnum (gdbarch)->fp0=0A= + + itype_rt (inst));=0A= + struct frame_info_ptr frame =3D get_current_frame ();=0A= + gdb_byte *raw_buffer =3D (gdb_byte *) alloca (sizeof (gdb_byt= e) * 4);=0A= + mips_read_fp_register_single (frame, fp, raw_buffer);=0A= +=0A= + if (gdbarch_byte_order (gdbarch) =3D=3D BFD_ENDIAN_BIG)=0A= + status =3D *(raw_buffer + 3);=0A= + else=0A= + status =3D *(raw_buffer);=0A= +=0A= + if (itype_rs (inst) =3D=3D 13)=0A= + true_val =3D 1;=0A= +=0A= + if ((status & 0x1) =3D=3D true_val)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 22 || op =3D=3D 23)=0A= + /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */=0A= + {=0A= + int rs =3D rtype_rs (inst);=0A= + int rt =3D rtype_rt (inst);=0A= + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs);=0A= + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt);=0A= + int taken =3D 0;=0A= + /* The R5 rt =3D=3D 0 case is handled above so we treat it as= =0A= + an unknown instruction here for future ISA usage. */=0A= + if (rs =3D=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rt <=3D 0);=0A= + else if (rs =3D=3D rt && rt !=3D 0)=0A= + taken =3D (val_rt >=3D 0);=0A= + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0)=0A= + taken =3D (val_rs >=3D val_rt);=0A= +=0A= + if (op =3D=3D 23)=0A= + taken =3D !taken;=0A= +=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated except= ions=0A= + we do not currently have access to the BD bit when hitti= ng a=0A= + breakpoint and therefore cannot tell if the breakpoint= =0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else if (op =3D=3D 50 || op =3D=3D 58)=0A= + /* BC, BALC */=0A= + pc +=3D mips32_relative_offset26 (inst) + 4;=0A= + else if ((op =3D=3D 54 || op =3D=3D 62)=0A= + && rtype_rs (inst) =3D=3D 0)=0A= + /* JIC, JIALC */=0A= + {=0A= + pc =3D regcache_raw_get_signed (regcache, itype_rt (inst));= =0A= + pc +=3D (itype_immediate (inst) ^ 0x8000) - 0x8000;=0A= + }=0A= + else if (op =3D=3D 54 || op =3D=3D 62)=0A= + /* BEQZC, BNEZC */=0A= + {=0A= + int rs =3D itype_rs (inst);=0A= + LONGEST rs_val =3D regcache_raw_get_signed (regcache, rs);=0A= + int taken =3D (rs_val =3D=3D 0);=0A= + if (op =3D=3D 62)=0A= + taken =3D !taken;=0A= + if (taken)=0A= + pc +=3D mips32_relative_offset21 (inst) + 4;=0A= + else=0A= + /* Step through the forbidden slot to avoid repeated except= ions=0A= + we do not currently have access to the BD bit when hitti= ng a=0A= + breakpoint and therefore cannot tell if the breakpoint= =0A= + hit on the branch or the forbidden slot. */=0A= + pc +=3D 8;=0A= + }=0A= + else=0A= + pc +=3D 4; /* Not a branch, next instruction is easy= . */=0A= + }=0A= else=0A= pc +=3D 4; /* Not a branch, next instruction is easy. */=0A= }=0A= @@ -1747,7 +1987,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc)=0A= case 2: /* BLTZL */=0A= case 16: /* BLTZAL */=0A= case 18: /* BLTZALL */=0A= - less_branch:=0A= if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)=0A= pc +=3D mips32_relative_offset (inst) + 4;=0A= else=0A= @@ -1763,22 +2002,38 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= pc +=3D 8; /* after the delay slot */=0A= break;=0A= case 0x1c: /* BPOSGE32 */=0A= + case 0x1d: /* BPOSGE32C */=0A= case 0x1e: /* BPOSGE64 */=0A= pc +=3D 4;=0A= if (itype_rs (inst) =3D=3D 0)=0A= {=0A= unsigned int pos =3D (op & 2) ? 64 : 32;=0A= int dspctl =3D mips_regnum (gdbarch)->dspctl;=0A= + int delay_slot_size =3D 4;=0A= =0A= if (dspctl =3D=3D -1)=0A= /* No way to handle; it'll most likely trap anyway. */=0A= break;=0A= =0A= + /* BPOSGE32C */=0A= + if (op =3D=3D 0x1d)=0A= + {=0A= + if (!is_mipsr6_isa (gdbarch))=0A= + break;=0A= +=0A= + /* Step through the forbidden slot to avoid repeate= d=0A= + exceptions we do not currently have access to th= e BD=0A= + bit when hitting a breakpoint and therefore cann= ot=0A= + tell if the breakpoint hit on the branch or the= =0A= + forbidden slot. */=0A= + /* delay_slot_size =3D 0; */=0A= + }=0A= +=0A= if ((regcache_raw_get_unsigned (regcache,=0A= dspctl) & 0x7f) >=3D pos)=0A= pc +=3D mips32_relative_offset (inst);=0A= else=0A= - pc +=3D 4;=0A= + pc +=3D delay_slot_size;=0A= }=0A= break;=0A= /* All of the other instructions in the REGIMM category */=0A= @@ -1812,19 +2067,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc)=0A= else=0A= pc +=3D 8;=0A= break;=0A= - case 6: /* BLEZ, BLEZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) <=3D 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */=0A= + lez_branch:=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 0);=0A= break;=0A= case 7:=0A= default:=0A= - greater_branch: /* BGTZ, BGTZL */=0A= - if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)=0A= - pc +=3D mips32_relative_offset (inst) + 4;=0A= - else=0A= - pc +=3D 8;=0A= + greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */=0A= + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 1);=0A= break;=0A= } /* switch */=0A= } /* else */=0A= @@ -2447,6 +2697,72 @@ micromips_instruction_is_compact_branch (unsigned sh= ort insn)=0A= }=0A= }=0A= =0A= +/* Return non-zero if the MIPS instruction INSN is a compact branch=0A= + or jump. A value of 1 indicates an unconditional compact branch=0A= + and a value of 2 indicates a conditional compact branch. */=0A= +=0A= +static int=0A= +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST in= sn)=0A= +{=0A= + switch (itype_op (insn))=0A= + {=0A= + /* BC */=0A= + case 50:=0A= + /* BALC */=0A= + case 58:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 1;=0A= + break;=0A= + /* BOVC, BEQZALC, BEQC */=0A= + case 8:=0A= + /* BNVC, BNEZALC, BNEC */=0A= + case 24:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + return 2;=0A= + break;=0A= + /* BEQZC, JIC */=0A= + case 54:=0A= + /* BNEZC, JIALC */=0A= + case 62:=0A= + if (is_mipsr6_isa (gdbarch))=0A= + /* JIC, JIALC are unconditional */=0A= + return (itype_rs (insn) =3D=3D 0) ? 1 : 2;=0A= + break;=0A= + /* BLEZC, BGEZC, BGEC */=0A= + case 22:=0A= + /* BGTZC, BLTZC, BLTC */=0A= + case 23:=0A= + /* BLEZALC, BGEZALC, BGEUC */=0A= + case 6:=0A= + /* BGTZALC, BLTZALC, BLTUC */=0A= + case 7:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) !=3D 0)=0A= + return 2;=0A= + break;=0A= + /* BPOSGE32C */=0A= + case 1:=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && itype_rt (insn) =3D=3D 0x1d && itype_rs (insn) =3D=3D 0)=0A= + return 2;=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +/* Return true if a standard MIPS instruction at ADDR has a branch=0A= + forbidden slot (i.e. it is a conditional compact branch instruction). = */=0A= +=0A= +static bool=0A= +mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR a= ddr)=0A= +{=0A= + int status;=0A= + ULONGEST insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &stat= us);=0A= + if (status)=0A= + return false;=0A= +=0A= + return mips32_instruction_is_compact_branch (gdbarch, insn) =3D=3D 2;=0A= +}=0A= +=0A= struct mips_frame_cache=0A= {=0A= CORE_ADDR base;=0A= @@ -2885,7 +3201,7 @@ mips_insn16_frame_cache (const frame_info_ptr &this_f= rame, void **this_cache)=0A= mips16_scan_prologue (gdbarch, start_addr, pc, this_frame,=0A= (struct mips_frame_cache *) *this_cache);=0A= }=0A= - =0A= +=0A= /* gdbarch_sp_regnum contains the value and not the address. */=0A= cache->saved_regs[gdbarch_num_regs (gdbarch)=0A= + MIPS_SP_REGNUM].set_value (cache->base);=0A= @@ -3422,7 +3738,7 @@ reset_saved_regs (struct gdbarch *gdbarch, struct mip= s_frame_cache *this_cache)=0A= }=0A= =0A= /* Analyze the function prologue from START_PC to LIMIT_PC. Builds=0A= - the associated FRAME_CACHE if not null. =0A= + the associated FRAME_CACHE if not null.=0A= Return the address of the first instruction past the prologue. */=0A= =0A= static CORE_ADDR=0A= @@ -3490,7 +3806,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= reg =3D high_word & 0x1f;=0A= =0A= if (high_word =3D=3D 0x27bd /* addiu $sp,$sp,-i */=0A= - || high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + || (high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */=0A= + && !is_mipsr6_isa (gdbarch))=0A= || high_word =3D=3D 0x67bd) /* daddiu $sp,$sp,-i */=0A= {=0A= if (offset < 0) /* Negative stack adjustment? */=0A= @@ -3628,7 +3945,9 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= =0A= /* A jump or branch, or enough non-prologue insns seen? If so,=0A= then we must have reached the end of the prologue by now. */=0A= - if (prev_delay_slot || non_prologue_insns > 1)=0A= + if (prev_delay_slot=0A= + || non_prologue_insns > 1=0A= + || mips32_instruction_is_compact_branch (gdbarch, inst))=0A= break;=0A= =0A= prev_non_prologue_insn =3D this_non_prologue_insn;=0A= @@ -3638,7 +3957,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= =0A= if (this_cache !=3D NULL)=0A= {=0A= - this_cache->base =3D =0A= + this_cache->base =3D=0A= (get_frame_register_signed (this_frame,=0A= gdbarch_num_regs (gdbarch) + frame_reg)=0A= + frame_offset);=0A= @@ -3657,7 +3976,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch,=0A= its address instead. */=0A= end_prologue_addr=0A= =3D prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;=0A= - =0A= +=0A= /* In a frameless function, we might have incorrectly=0A= skipped some load immediate instructions. Undo the skipping=0A= if the load immediate was not followed by a stack adjustment. */=0A= @@ -3701,7 +4020,7 @@ mips_insn32_frame_cache (const frame_info_ptr &this_f= rame, void **this_cache)=0A= mips32_scan_prologue (gdbarch, start_addr, pc, this_frame,=0A= (struct mips_frame_cache *) *this_cache);=0A= }=0A= - =0A= +=0A= /* gdbarch_sp_regnum contains the value and not the address. */=0A= cache->saved_regs[gdbarch_num_regs (gdbarch)=0A= + MIPS_SP_REGNUM].set_value (cache->base);=0A= @@ -3924,7 +4243,7 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_= ADDR addr)=0A= =0A= /* Checks for an atomic sequence of instructions beginning with a LL/LLD= =0A= instruction and ending with a SC/SCD instruction. If such a sequence= =0A= - is found, attempt to step through it. A breakpoint is placed at the en= d of =0A= + is found, attempt to step through it. A breakpoint is placed at the en= d of=0A= the sequence. */=0A= =0A= /* Instructions used during single-stepping of atomic sequences, standard= =0A= @@ -3933,6 +4252,70 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE= _ADDR addr)=0A= #define LLD_OPCODE 0x34=0A= #define SC_OPCODE 0x38=0A= #define SCD_OPCODE 0x3c=0A= +#define LLSC_R6_OPCODE 0x1f=0A= +#define LL_R6_FUNCT 0x36=0A= +#define LLE_FUNCT 0x2e=0A= +#define LLD_R6_FUNCT 0x37=0A= +#define SC_R6_FUNCT 0x26=0A= +#define SCE_FUNCT 0x1e=0A= +#define SCD_R6_FUNCT 0x27=0A= +=0A= +/* Determine whether instruction 'insn' is of 'load linked X' type.=0A= + LL/SC instructions provide primitives to implement atomic=0A= + read-modify-write operations for synchronizable memory locations. */= =0A= +=0A= +static bool=0A= +is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D LL_OPCODE=0A= + || itype_op (insn) =3D=3D LLD_OPCODE)=0A= + return true;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D LLE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return true;=0A= +=0A= + /* Handle LL and LLP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D LL_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D LLE_FUNCT))=0A= + return true;=0A= +=0A= + return false;=0A= +}=0A= +=0A= +/* Determine whether instruction 'insn' is of 'store conditional X' type.= =0A= + SC instructions and varieties perform completion of read-modify-write= =0A= + atomic sequence. */=0A= +=0A= +static bool=0A= +is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn)=0A= +{=0A= + if (itype_op (insn) =3D=3D SC_OPCODE=0A= + || itype_op (insn) =3D=3D SCD_OPCODE)=0A= + return true;=0A= +=0A= + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && rtype_funct (insn) =3D=3D SCE_FUNCT=0A= + && (insn & 0x40) =3D=3D 0)=0A= + return true;=0A= +=0A= + /* Handle SC and SCP varieties. */=0A= + if (is_mipsr6_isa (gdbarch)=0A= + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE=0A= + && (rtype_funct (insn) =3D=3D SC_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCD_R6_FUNCT=0A= + || rtype_funct (insn) =3D=3D SCE_FUNCT))=0A= + return true;=0A= +=0A= + return false;=0A= +}=0A= +=0A= +/* Handle mips atomic sequence which starts with LL/LLD and ends with=0A= + SC/SCD instruction. */=0A= =0A= static std::vector=0A= mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= @@ -3943,15 +4326,16 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= ULONGEST insn;=0A= int insn_count;=0A= int index;=0A= - int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =0A= + int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =0A= const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */=0A= + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);=0A= /* Assume all atomic sequences start with a ll/lld instruction. */=0A= - if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE)= =0A= + if (!is_ll_insn (gdbarch, insn))=0A= return {};=0A= =0A= - /* Assume that no atomic sequence is longer than "atomic_sequence_length= " =0A= + /* Assume that no atomic sequence is longer than "atomic_sequence_length= "=0A= instructions. */=0A= for (insn_count =3D 0; insn_count < atomic_sequence_length; ++insn_count= )=0A= {=0A= @@ -3978,28 +4362,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= return {}; /* fallback to the standard single-step code. */=0A= case 4: /* BEQ */=0A= case 5: /* BNE */=0A= - case 6: /* BLEZ */=0A= - case 7: /* BGTZ */=0A= case 20: /* BEQL */=0A= case 21: /* BNEL */=0A= - case 22: /* BLEZL */=0A= - case 23: /* BGTTL */=0A= + case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */=0A= + case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */=0A= is_branch =3D 1;=0A= break;=0A= + case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */=0A= + case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */=0A= + if (is_mipsr6)=0A= + {=0A= + /* BLEZALC, BGTZALC */=0A= + if (itype_rs (insn) =3D=3D 0 && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. *= /=0A= + /* BGEZALC, BLTZALC */=0A= + else if (itype_rs (insn) =3D=3D itype_rt (insn)=0A= + && itype_rt (insn) !=3D 0)=0A= + return {}; /* fallback to the standard single-step code. *= /=0A= + }=0A= + is_branch =3D 1;=0A= + break;=0A= + case 8: /* BOVC, BEQZALC, BEQC */=0A= + case 24: /* BNVC, BNEZALC, BNEC */=0A= + if (is_mipsr6)=0A= + is_branch =3D 1;=0A= + break;=0A= + case 50: /* BC */=0A= + case 58: /* BALC */=0A= + if (is_mipsr6)=0A= + return {}; /* fallback to the standard single-step code. */=0A= + break;=0A= + case 54: /* BEQZC, JIC */=0A= + case 62: /* BNEZC, JIALC */=0A= + if (is_mipsr6)=0A= + {=0A= + if (itype_rs (insn) =3D=3D 0) /* JIC, JIALC */=0A= + return {}; /* fallback to the standard single-step code. *= /=0A= + else=0A= + is_branch =3D 2; /* Marker for branches with a 21-bit offse= t. */=0A= + }=0A= + break;=0A= case 17: /* COP1 */=0A= - is_branch =3D ((itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10)= =0A= - && (itype_rt (insn) & 0x2) =3D=3D 0);=0A= - if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + is_branch =3D ((!is_mipsr6=0A= + /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */=0A= + && (itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D= =3D 10)=0A= + && (itype_rt (insn) & 0x2) =3D=3D 0)=0A= + /* BZ.df: 010001 110xx */=0A= + || (itype_rs (insn) & 0x18) =3D=3D 0x18);=0A= + if (is_branch !=3D 0)=0A= break;=0A= [[fallthrough]];=0A= case 18: /* COP2 */=0A= case 19: /* COP3 */=0A= - is_branch =3D (itype_rs (insn) =3D=3D 8); /* BCzF, BCzFL, BCzT, BCzTL *= /=0A= + /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */=0A= + is_branch =3D ((itype_rs (insn) =3D=3D 8)=0A= + || (is_mipsr6=0A= + && (itype_rs (insn) =3D=3D 9=0A= + || itype_rs (insn) =3D=3D 13)));=0A= break;=0A= }=0A= - if (is_branch)=0A= + if (is_branch !=3D 0)=0A= {=0A= - branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= + /* Is this a special PC21_S2 branch? */=0A= + if (is_branch =3D=3D 2)=0A= + branch_bp =3D loc + mips32_relative_offset21 (insn) + 4;=0A= + else=0A= + branch_bp =3D loc + mips32_relative_offset (insn) + 4;=0A= if (last_breakpoint >=3D 1)=0A= return {}; /* More than one branch found, fallback to the=0A= standard single-step code. */=0A= @@ -4007,12 +4435,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc)=0A= last_breakpoint++;=0A= }=0A= =0A= - if (itype_op (insn) =3D=3D SC_OPCODE || itype_op (insn) =3D=3D SCD_O= PCODE)=0A= + if (is_sc_insn (gdbarch, insn))=0A= break;=0A= }=0A= =0A= /* Assume that the atomic sequence ends with a sc/scd instruction. */= =0A= - if (itype_op (insn) !=3D SC_OPCODE && itype_op (insn) !=3D SCD_OPCODE)= =0A= + if (!is_sc_insn (gdbarch, insn))=0A= return {};=0A= =0A= loc +=3D MIPS_INSN32_SIZE;=0A= @@ -4161,7 +4589,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *= gdbarch,=0A= }=0A= break;=0A= }=0A= - if (is_branch)=0A= + if (is_branch !=3D 0)=0A= {=0A= if (last_breakpoint >=3D 1)=0A= return {}; /* More than one branch found, fallback to the=0A= @@ -4237,8 +4665,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_= ADDR pc)=0A= gdb_assert (mips_pc_is_mips (pc));=0A= =0A= insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);=0A= - hint =3D 0x7c0;=0A= - return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */=0A= + /* Mask the hint and the jalr/jr bit. */=0A= + hint =3D 0x7c1;=0A= +=0A= + if (is_mipsr6_isa (gdbarch) && insn =3D=3D 0xd81f0000) /* jrc $31 */=0A= + return 1;=0A= +=0A= + /* jr(.hb) $ra and "jalr(.hb) $ra" */=0A= + return ((insn & ~hint) =3D=3D 0x3e00008);=0A= }=0A= =0A= =0A= @@ -4814,7 +5248,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function,=0A= {=0A= if (type->code () =3D=3D TYPE_CODE_FLT)=0A= fp_return_type =3D 1;=0A= - /* Structs with a single field of float type =0A= + /* Structs with a single field of float type=0A= are returned in a floating point register. */=0A= if ((type->code () =3D=3D TYPE_CODE_STRUCT=0A= || type->code () =3D=3D TYPE_CODE_UNION)=0A= @@ -4827,7 +5261,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function,=0A= }=0A= }=0A= =0A= - if (fp_return_type) =0A= + if (fp_return_type)=0A= {=0A= /* A floating-point value belongs in the least significant part=0A= of FP0/FP1. */=0A= @@ -4835,7 +5269,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function,=0A= gdb_printf (gdb_stderr, "Return float in $fp0\n");=0A= regnum =3D mips_regnum (gdbarch)->fp0;=0A= }=0A= - else =0A= + else=0A= {=0A= /* An integer value goes in V0/V1. */=0A= if (mips_debug)=0A= @@ -6755,7 +7189,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbar= ch, CORE_ADDR pc)=0A= =0A= if (high_word !=3D 0x27bd /* addiu $sp,$sp,offset */=0A= && high_word !=3D 0x67bd /* daddiu $sp,$sp,offset */=0A= - && inst !=3D 0x03e00008 /* jr $ra */=0A= + && (inst & ~0x1) !=3D 0x03e00008 /* jr $31 or jalr $0, $31 *= /=0A= + && (!is_mipsr6_isa (gdbarch)=0A= + || inst !=3D 0xd81f0000) /* jrc $31 */=0A= && inst !=3D 0x00000000) /* nop */=0A= return 0;=0A= }=0A= @@ -7134,22 +7570,31 @@ mips32_instruction_has_delay_slot (struct gdbarch *= gdbarch, ULONGEST inst)=0A= int op;=0A= int rs;=0A= int rt;=0A= + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch);=0A= =0A= op =3D itype_op (inst);=0A= if ((inst & 0xe0000000) !=3D 0)=0A= {=0A= rs =3D itype_rs (inst);=0A= rt =3D itype_rt (inst);=0A= - return (is_octeon_bbit_op (op, gdbarch) =0A= - || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */=0A= - || op =3D=3D 29 /* JALX: bits 011101 */=0A= + return (is_octeon_bbit_op (op, gdbarch)=0A= + || (op >> 1 =3D=3D 10) /* BEQL, BNEL: bits 01010x */=0A= + || (op >> 1 =3D=3D 11 && rt =3D=3D 0) /* BLEZL, BGTZL: bits 0= 1011x */=0A= + || (!is_mipsr6 && op =3D=3D 29) /* JALX: bits 011101 *= /=0A= || (op =3D=3D 17=0A= && (rs =3D=3D 8=0A= /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */=0A= - || (rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)=0A= + || (!is_mipsr6 && rs =3D=3D 9 && (rt & 0x2) =3D=3D 0)= =0A= /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */=0A= - || (rs =3D=3D 10 && (rt & 0x2) =3D=3D 0))));=0A= + || (!is_mipsr6 && rs =3D=3D 10 && (rt & 0x2) =3D=3D 0= )))=0A= /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */=0A= + || (is_mipsr6=0A= + && ((op =3D=3D 17=0A= + && (rs =3D=3D 9 /* BC1EQZ: 010001 01001 */=0A= + || rs =3D=3D 13)) /* BC1NEZ: 010001 01101 */= =0A= + || (op =3D=3D 18=0A= + && (rs =3D=3D 9 /* BC2EQZ: 010010 01001 */=0A= + || rs =3D=3D 13))))); /* BC2NEZ: 010010 0110= 1 */=0A= }=0A= else=0A= switch (op & 0x07) /* extract bits 28,27,26 */=0A= @@ -7168,7 +7613,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *g= dbarch, ULONGEST inst)=0A= || ((rt & 0x1e) =3D=3D 0x1c && rs =3D=3D 0));=0A= /* BPOSGE32, BPOSGE64: bits 1110x */=0A= break; /* end REGIMM */=0A= - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */=0A= + case 6: /* BLEZ */=0A= + case 7: /* BGTZ */=0A= + return (itype_rt (inst) =3D=3D 0);=0A= + break;=0A= + default: /* J, JAL, BEQ, BNE */=0A= return 1;=0A= break;=0A= }=0A= @@ -7346,7 +7795,7 @@ mips_segment_boundary (CORE_ADDR bpaddr)=0A= }=0A= =0A= /* Move the breakpoint at BPADDR out of any branch delay slot by shifting= =0A= - it backwards if necessary. Return the address of the new location. */= =0A= + it backwards if necessary. Return the address of the new location. */= =0A= =0A= static CORE_ADDR=0A= mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)= =0A= @@ -7380,7 +7829,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= =0A= So, we'll use the second solution. To do this we need to know if=0A= the instruction we're trying to set the breakpoint on is in the=0A= - branch delay slot. */=0A= + branch delay slot.=0A= +=0A= + A similar problem occurs for breakpoints on forbidden slots where=0A= + the trap will be reported for the branch with the BD bit set.=0A= + In this case it would be ideal to recover using solution 1 from=0A= + above as there is no problem with the branch being skipped=0A= + (since the forbidden slot only exists on not-taken branches).=0A= + However, the BD bit is not available in all scenarios currently=0A= + so instead we move the breakpoint on to the next instruction.=0A= + This means that it is not possible to stop on an instruction=0A= + that can be in a forbidden slot even if that instruction is=0A= + jumped to directly. */=0A= =0A= boundary =3D mips_segment_boundary (bpaddr);=0A= =0A= @@ -7402,6 +7862,12 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr)=0A= prev_addr =3D bpaddr - 4;=0A= if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))=0A= bpaddr =3D prev_addr;=0A= + /* If the previous instruction has a forbidden slot, we have to=0A= + move the breakpoint to the following instruction to prevent=0A= + breakpoints in forbidden slots being reported as unknown=0A= + traps. */=0A= + else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr))= =0A= + bpaddr +=3D 4;=0A= }=0A= else=0A= {=0A= @@ -8826,7 +9292,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct g= dbarch_list *arches)=0A= =0A= for (i =3D 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)=0A= user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,=0A= - value_of_mips_user_reg, =0A= + value_of_mips_user_reg,=0A= &mips_numeric_register_aliases[i].regnum);=0A= =0A= return gdbarch;=0A= @@ -8854,7 +9320,7 @@ show_mips_abi (struct ui_file *file,=0A= if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch=0A= !=3D bfd_arch_mips)=0A= gdb_printf=0A= - (file, =0A= + (file,=0A= "The MIPS ABI is unknown because the current architecture "=0A= "is not MIPS.\n");=0A= else=0A= @@ -8865,7 +9331,7 @@ show_mips_abi (struct ui_file *file,=0A= =0A= if (global_abi =3D=3D MIPS_ABI_UNKNOWN)=0A= gdb_printf=0A= - (file, =0A= + (file,=0A= "The MIPS ABI is set automatically (currently \"%s\").\n",=0A= actual_abi_str);=0A= else if (global_abi =3D=3D actual_abi)=0A= @@ -9117,3 +9583,4 @@ When non-zero, mips specific debugging is enabled."),= =0A= currently %s. */=0A= &setdebuglist, &showdebuglist);=0A= }=0A= +=0A= diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.c b/gdb/testsuite/gdb.arch/m= ips-64-r6.c=0A= new file mode 100644=0A= index 00000000000..13f43ee24d0=0A= --- /dev/null=0A= +++ b/gdb/testsuite/gdb.arch/mips-64-r6.c=0A= @@ -0,0 +1,918 @@=0A= +/*=0A= + Copyright 2023-2024 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see .= =0A= +*/=0A= +=0A= +#define xstr(s) str(s)=0A= +#define str(s) #s=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/uti= ls-r6.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +/* 58 is local label to exit with errcode !=3D 0, indicating error. */=0A= +#define fp_assert(a, b) "beq " xstr (a) ", " xstr (b) ", 1f \n\t" \=0A= + "nop \n\t" \=0A= + "b 58f \n\t" \=0A= + "nop \n\t" \=0A= + "1: \n\t"=0A= +=0A= +/* Clobbers: $4,$6,$7. */=0A= +#define r6ck_1r(inst, a, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4 \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$6,$7. */=0A= +#define r6ck_1dr(inst, a, ret) \=0A= + "ld $4, " xstr (a) " \n\t" \=0A= + "ld $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4 \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7. */=0A= +#define r6ck_2r(inst, a, b, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $5, " xstr (b) " \n\t" \=0A= + "li $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, $5 \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7. */=0A= +#define r6ck_2dr(inst, a, b, ret) \=0A= + "ld $4, " xstr (a) " \n\t" \=0A= + "ld $5, " xstr (b) " \n\t" \=0A= + "ld $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, $5 \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7. */=0A= +#define r6ck_2dr1i(inst, a, b, imm, ret) \=0A= + "ld $4, " xstr (a) " \n\t" \=0A= + "ld $5, " xstr (b) " \n\t" \=0A= + "ld $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$6,$7. */=0A= +#define r6ck_1r1i(inst, a, imm, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, " xstr (imm) " \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$6,$7. */=0A= +#define r6ck_1dr1i(inst, a, imm, ret) \=0A= + "ld $4, " xstr (a) " \n\t" \=0A= + "ld $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, " xstr (imm) " \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$6. */=0A= +#define r6ck_0dr1i(inst, a, imm, ret) \=0A= + "ld $4, " xstr (a) " \n\t" \=0A= + "ld $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $4, $4, " xstr (imm) " \n\t" \=0A= + fp_assert ($6, $4)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7. */=0A= +#define r6ck_2r1i(inst, a, b, imm, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $5, " xstr (b) " \n\t" \=0A= + "li $6, " xstr (ret) " \n\t" \=0A= + xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7,$8,$f2,$f4,$f6. */=0A= +#define r6ck_3s(inst, a, b, c, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $5, " xstr (b) " \n\t" \=0A= + "li $6, " xstr (c) " \n\t" \=0A= + "li $7, " xstr (ret) " \n\t" \=0A= + "mtc1 $4, $f2 \n\t" \=0A= + "mtc1 $5, $f4 \n\t" \=0A= + "mtc1 $6, $f6 \n\t" \=0A= + xstr (inst) " $f2, $f4, $f6 \n\t" \=0A= + "mfc1 $8, $f2 \n\t" \=0A= + fp_assert ($7, $8)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7,$f2,$f4. */=0A= +#define r6ck_2s(inst, a, b, ret) \=0A= + "li $4, " xstr (a) " \n\t" \=0A= + "li $5, " xstr (b) " \n\t" \=0A= + "li $6, " xstr (ret) " \n\t" \=0A= + "mtc1 $4, $f2 \n\t" \=0A= + "mtc1 $5, $f4 \n\t" \=0A= + xstr (inst) " $f2, $f4 \n\t" \=0A= + "mfc1 $7, $f2 \n\t" \=0A= + fp_assert ($6, $7)=0A= +=0A= +/* Clobbers: $4,$5,$6,$7,$8,$9,$10,$f2,$f4. */=0A= +#define r6ck_2d(inst, a, b, ret) \=0A= + ".data \n\t" \=0A= + "1: .dword " xstr (a) " \n\t" \=0A= + "2: .dword " xstr (b) " \n\t" \=0A= + "3: .dword " xstr (ret) " \n\t" \=0A= + ".text \n\t" \=0A= + "dla $4, 1b \n\t" \=0A= + "dla $5, 2b \n\t" \=0A= + "dla $6, 3b \n\t" \=0A= + "ldc1 $f2, 0($4) \n\t" \=0A= + "ldc1 $f4, 0($5) \n\t" \=0A= + "lw $7, 0($6) \n\t" \=0A= + "lw $8, 4($6) \n\t" \=0A= + xstr (inst) " $f2, $f4 \n\t" \=0A= + "mfhc1 $9, $f2 \n\t" \=0A= + "mfc1 $10, $f2 \n\t" \=0A= + fp_assert ($7, $9) \=0A= + fp_assert ($8, $10)=0A= +=0A= +/* Clobbers: $2,$4,$5,$6,$7,$8,$9,$10,$f2,$f4,$f6. */=0A= +#define r6ck_3d(inst, a, b, c, ret) \=0A= + ".data \n\t" \=0A= + "1: .dword " xstr (a) " \n\t" \=0A= + "2: .dword " xstr (b) " \n\t" \=0A= + "3: .dword " xstr (c) " \n\t" \=0A= + "4: .dword " xstr (ret) " \n\t" \=0A= + ".text \n\t" \=0A= + "dla $4, 1b \n\t" \=0A= + "dla $5, 2b \n\t" \=0A= + "dla $6, 3b \n\t" \=0A= + "dla $2, 4b \n\t" \=0A= + "ldc1 $f2, 0($4) \n\t" \=0A= + "ldc1 $f4, 0($5) \n\t" \=0A= + "ldc1 $f6, 0($6) \n\t" \=0A= + "lw $7, 0($2) \n\t" \=0A= + "lw $8, 4($2) \n\t" \=0A= + xstr (inst) " $f2, $f4, $f6 \n\t" \=0A= + "mfhc1 $9, $f2 \n\t" \=0A= + "mfc1 $10, $f2 \n\t" \=0A= + fp_assert ($7, $9) \=0A= + fp_assert ($8, $10)=0A= +=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/tes= tutils.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +/* Put value 'val' into register 'reg'.=0A= + Clobbers: None. */=0A= +#define load32(reg, val) \=0A= + "li " xstr (reg) ", " xstr (val) " \n\t"=0A= +=0A= +/* Check whether two registers contain the same value.=0A= + Clobbers: None. */=0A= +#define checkreg(reg, expreg) \=0A= + ".set push \n\t" \=0A= + ".set noat \n\t" \=0A= + ".set noreorder \n\t" \=0A= + "beq " xstr (expreg) ", " xstr (reg) ", 901f \n\t" \=0A= + "nop \n\t" \=0A= + "b 58f \n\t" \=0A= + "nop \n\t" \=0A= + "901: \n\t" \=0A= + ".set pop \n\t"=0A= +=0A= +/* Check if register 'reg' contains value 'val'.=0A= + Clobbers: $1. */=0A= +#define check32(reg, val) \=0A= + ".set push \n\t" \=0A= + ".set noat \n\t" \=0A= + load32 ($1, val) \=0A= + checkreg (reg, $1) \=0A= + ".set pop \n\t"=0A= +=0A= +/* Checkpair based on endianess=0A= + Clobbers: $1. */=0A= +#define checkpair_xendian(lo, hi, base, ec, w) \=0A= + ".set noat \n\t" \=0A= + "lw $1, " xstr (ec) " \n\t" \=0A= + "andi $1, $1, 0x1 \n\t" \=0A= + "beqz $1, 2f \n\t" \=0A= + ".set at \n\t" \=0A= + "1: \n\t" \=0A= + checkpair_be_##w (lo, hi, base) \=0A= + "b 3f \n\t" \=0A= + "nop \n\t" \=0A= + "2: \n\t" \=0A= + checkpair_le_##w (lo, hi, base) \=0A= + "3: \n\t"=0A= +=0A= +=0A= +/* Check hi-lo register pair against data stored at base+o1 and base+o2.= =0A= + Clobbers: $1 - $5. */=0A= +#define checkpair(lo, hi, base, w, o1, o2) \=0A= + "move $2, " xstr (lo) " \n\t" \=0A= + "move $3, " xstr (hi) " \n\t" \=0A= + ".set noat \n\t" \=0A= + "dla $1, " xstr (base) " \n\t" \=0A= + "l" xstr (w) " $4, " xstr (o1) "($1) \n\t" \=0A= + "l" xstr (w) " $5, " xstr (o2) "($1) \n\t" \=0A= + ".set at \n\t" \=0A= + checkreg ($2, $4) \=0A= + checkreg ($3, $5)=0A= +=0A= +#define checkpair_le_d(lo, hi, base) \=0A= + checkpair (lo, hi, base, w, 0, 4)=0A= +=0A= +#define checkpair_be_d(lo, hi, base) \=0A= + checkpair (lo, hi, base, w, 4, 0)=0A= +=0A= +=0A= +#define checkpair_le_q(lo, hi, base) \=0A= + checkpair (lo, hi, base, d, 0, 8)=0A= +=0A= +#define checkpair_be_q(lo, hi, base) \=0A= + checkpair (lo, hi, base, d, 8, 0)=0A= +=0A= +#define checkpair_qword(lo, hi, base, oe) \=0A= + checkpair_xendian (lo, hi, base, oe, q)=0A= +=0A= +#define checkpair_dword(lo, hi, base, oe) \=0A= + checkpair_xendian (lo, hi, base, oe, d)=0A= +=0A= +void=0A= +abort (void);=0A= +=0A= +/* Tests branch instructions. */=0A= +=0A= +int=0A= +test_r6_branch (void)=0A= +{=0A= +/* Using volatile to prevent certain optimizations which could cause=0A= + * instruction deletion.=0A= + * 'err' identifies instruction which (eventually) caused error.=0A= + * (err =3D=3D 0) =3D=3D> all instructions executed successfully. */=0A= +=0A= + volatile int err =3D -1;=0A= + volatile int a14 =3D 0xffffffff;=0A= + volatile int a13 =3D 0x123;=0A= + volatile int a12 =3D 0x45;=0A= + volatile int a7 =3D 0x45;=0A= + volatile int a8 =3D 0xfffffffe;=0A= + volatile int a9 =3D 2147483647;=0A= + volatile int a11 =3D 0;=0A= + volatile int a10 =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t" /* Create new scope for asm configuration. = */=0A= + ".set noreorder \n\t" /* Don't allow reordering of instructions. = */=0A= + "li %[err], 1 \n\t"=0A= + "bovc %[a12], %[a13], Lfail \n\t" /* BOVC */=0A= + "nop \n\t"=0A= + "bovc %[a9], %[a13], L2 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L2: \n\t"=0A= + "li %[err], 2 \n\t"=0A= + "bnvc %[a9], %[a13], Lfail \n\t" /* BNVC */=0A= + "nop \n\t"=0A= + "bnvc %[a12], %[a13], L3 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L3: \n\t"=0A= + "li %[err], 3 \n\t"=0A= + "beqc %[a12], %[a13], Lfail \n\t" /* BEQC */=0A= + "nop \n\t"=0A= + "beqc %[a12], %[a7], L4 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L4: \n\t"=0A= + "li %[err], 4 \n\t"=0A= + "bnec %[a12], %[a7], Lfail \n\t" /* BNEC */=0A= + "nop \n\t"=0A= + "bnec %[a12], %[a13], L5 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L5: \n\t"=0A= + "li %[err], 5 \n\t"=0A= + "bltc %[a13], %[a12], Lfail \n\t" /* BLTC */=0A= + "nop \n\t"=0A= + "bltc %[a12], %[a13], L6 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L6: \n\t"=0A= + "L7: \n\t"=0A= + "li %[err], 7 \n\t"=0A= + "bgec %[a12], %[a13], Lfail \n\t" /* BGEC */=0A= + "nop \n\t"=0A= + "bgec %[a13], %[a12], L8 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L8: \n\t"=0A= + "L9: \n\t"=0A= + "li %[err], 9 \n\t"=0A= + "bltuc %[a14], %[a13], Lfail \n\t" /* BLTUC */=0A= + "nop \n\t"=0A= + "bltuc %[a8], %[a14], L10 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L10: \n\t"=0A= + "L11: \n\t"=0A= + "li %[err], 11 \n\t"=0A= + "bgeuc %[a13], %[a14], Lfail \n\t" /* BGEUC */=0A= + "nop \n\t"=0A= + "bgeuc %[a14], %[a8], L12 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L12: \n\t"=0A= + "L13: \n\t"=0A= + "li %[err], 13 \n\t"=0A= + "bltzc %[a13], Lfail \n\t" /* BLTZC */=0A= + "nop \n\t"=0A= + "bltzc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bltzc %[a14], L14 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L14: \n\t"=0A= + "li %[err], 14 \n\t"=0A= + "blezc %[a13], Lfail \n\t" /* BLEZC */=0A= + "nop \n\t"=0A= + "blezc %[a11], L145 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L145: \n\t"=0A= + "blezc %[a14], L15 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L15: \n\t"=0A= + "li %[err], 15 \n\t"=0A= + "bgezc %[a8], Lfail \n\t" /* BGEZC */=0A= + "nop \n\t"=0A= + "bgezc %[a11], L155 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L155: \n\t"=0A= + "bgezc %[a13], L16 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L16: \n\t"=0A= + "li %[err], 16 \n\t"=0A= + "bgtzc %[a8], Lfail \n\t" /* BGTZC */=0A= + "nop \n\t"=0A= + "bgtzc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bgtzc %[a13], L17 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "L17: \n\t"=0A= + "li %[err], 17 \n\t"=0A= + "blezalc %[a12], Lfail \n\t" /* BLEZALC */=0A= + "nop \n\t"=0A= + "blezalc %[a11], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L175 \n\t" /* BEQZC */=0A= + "nop \n\t"=0A= + "li %[err], 8531 \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L175: \n\t"=0A= + "li %[err], 23531 \n\t"=0A= + "blezalc %[a14], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L18 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L18: \n\t"=0A= + "li %[err], 18 \n\t"=0A= + "bgezalc %[a14], Lfail \n\t" /* BGEZALC */=0A= + "nop \n\t"=0A= + "bgezalc %[a11], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L185 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L185: \n\t"=0A= + "bgezalc %[a12], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L19 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L19: \n\t"=0A= + "li %[err], 19 \n\t"=0A= + "bgtzalc %[a14], Lfail \n\t" /* BGTZALC */=0A= + "nop \n\t"=0A= + "bgtzalc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bgtzalc %[a12], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L20 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L20: \n\t"=0A= + "li %[err], 20 \n\t"=0A= + "bltzalc %[a12], Lfail \n\t" /* BLTZALC */=0A= + "nop \n\t"=0A= + "bltzalc %[a11], Lfail \n\t"=0A= + "nop \n\t"=0A= + "bltzalc %[a14], Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L21 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L21: \n\t"=0A= + "li %[err], 21 \n\t"=0A= + "bc L22 \n\t" /* BC */=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L22: \n\t"=0A= + "li %[err], 22 \n\t"=0A= + "balc Lret \n\t" /* BALC */=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], L23 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L23: \n\t"=0A= + "li %[err], 23 \n\t"=0A= + "jal GetPC \n\t" /* JAL */=0A= + "nop \n\t"=0A= + "jic $6, 4 \n\t" /* JIC */=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L24: \n\t"=0A= + "li %[err], 24 \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "jal GetPC \n\t"=0A= + "nop \n\t"=0A= + "jialc $6, 20 \n\t" /* JIALC */=0A= + "nop \n\t"=0A= + "beqzc %[a10], L25 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "LJIALCRET: \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "jr $31 \n\t" /* JR */=0A= + "nop \n\t"=0A= + "L25: \n\t"=0A= + "li %[err], 25 \n\t"=0A= + "jal GetPC \n\t"=0A= + "nop \n\t"=0A= + "move %[a11], $6 \n\t"=0A= + "nal \n\t"=0A= + "nop \n\t"=0A= + "addiu %[a11], 12 \n\t" /* ADDIU */=0A= + "beqc %[a11], $31, L26 \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "L26: \n\t"=0A= + "li %[err], 26 \n\t"=0A= + "balc Lret \n\t"=0A= + "li %[a10], 1 \n\t"=0A= + "beqzc %[a10], Lend \n\t"=0A= + "nop \n\t"=0A= + "b Lfail \n\t"=0A= + "nop \n\t"=0A= + "Lret: \n\t"=0A= + "li %[a10], 0 \n\t"=0A= + "daddiu $31, 4 \n\t" /* DADDIU */=0A= + "jrc $31 \n\t" /* JRC */=0A= + "nop \n\t"=0A= + "GetPC: \n\t"=0A= + "move $6, $31 \n\t"=0A= + "jr $31 \n\t"=0A= + "Lend: \n\t"=0A= + "li %[err], 0 \n\t"=0A= + "Lfail: \n\t"=0A= + ".set pop \n\t" /* Restore previous config */=0A= + : [err] "+r"(err), [a14] "+r"(a14), [a13] "+r"(a13), [a12] "+r"(a12),=0A= + [a7] "+r"(a7), [a8] "+r"(a8), [a9] "+r"(a9), [a10] "+r"(a10), [a11] "+= r"(a11)=0A= + : /* inputs */=0A= + : "$31", "$6" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +/* Tests forbidden slot branching i.e. conditional compact branch=0A= + instructions. */=0A= +=0A= +int=0A= +test_r6_forbidden (void)=0A= +{=0A= + volatile int err =3D -1;=0A= + volatile int a4 =3D 0;=0A= + volatile int a2 =3D 0;=0A= + volatile int a1 =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= +/* Test if FS is ignored when branch is taken */=0A= + "li %[err], 1 \n\t"=0A= + "li %[a4], 0 \n\t"=0A= + "beqzalc %[a4], L41 \n\t"=0A= + "li %[err], -85 \n\t"=0A= + "L42: \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "L41: \n\t"=0A= + "blez %[err], Lfail2 \n\t"=0A= +/* Test if FS is used when branch is not taken */=0A= + "li %[err], 2 \n\t"=0A= + "li %[a4], 1 \n\t"=0A= + "blezc %[a4], L43 \n\t"=0A= + "addiu %[a4], %[a4], 1 \n\t"=0A= + "li %[a2], 2 \n\t"=0A= + "beq %[a4], %[a2], L44 \n\t"=0A= + "nop \n\t"=0A= + "L43: \n\t"=0A= + "nop \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "L44: \n\t"=0A= + "li %[err], 3 \n\t"=0A= + "li %[a4], 3 \n\t"=0A= + "beqzalc %[a4], Lfail2 \n\t"=0A= +/* Note: 'bc L45' instead nop would cause SegFault: Illegal instruction:= =0A= + Forbidden slot causes an error when it contains a branch. */=0A= + "nop \n\t"=0A= + "b Lend2 \n\t"=0A= + "nop \n\t"=0A= + "L45: \n\t"=0A= + "nop \n\t"=0A= + "b Lfail2 \n\t"=0A= + "nop \n\t"=0A= + "Lend2: \n\t"=0A= + "li %[err], 0 \n\t"=0A= + "Lfail2: \n\t"=0A= + "nop \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r" (err), [a4] "+r"(a4), [a2] "+r"(a2), [a1] "+r"(a1) /* outpu= ts */=0A= + : /* inputs */=0A= + : "$31" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +int=0A= +test_r6_64 (void)=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + "dval: .dword 0xaa55bb66cc77dd88 \n\t"=0A= + "d1: .dword 0xaaaabbbbccccdddd \n\t"=0A= + "d5: .dword 0x00000000000000dd \n\t"=0A= + "d7: .dword 0xeeeeffff00001111 \n\t"=0A= + "d8: .dword 0xbbccccddddeeeeff \n\t"=0A= + "d9: .dword 0x000000ddaaaabbbb \n\t"=0A= + "dval1: .word 0x1234abcd \n\t"=0A= + "dval2: .word 0xffee0000 \n\t"=0A= + "dval3: .dword 0xffffffffffffffff \n\t"=0A= + " .fill 240,1,0 \n\t"=0A= + "dval4: .dword 0x5555555555555555 \n\t"=0A= + " .fill 264,1,0 \n\t"=0A= +=0A= +/* Register $11 stores instruction currently being tested and hence=0A= + * identifies error if it occurs. */=0A= + ".text \n\t"=0A= +=0A= + "li $11, 1 \n\t" /* Test DALIGN */=0A= + r6ck_2dr1i (dalign, d7, d1, 3, d8)=0A= + r6ck_2dr1i (dalign, d1, d5, 4, d9)=0A= +=0A= + "li $11, 2 \n\t" /* Test LDPC */=0A= + "ld $5, dval \n\t"=0A= + "nop \n\t"=0A= + "ldpc $4, dval \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 3 \n\t" /* Test LWUPC */=0A= + "lwu $5, dval1 \n\t"=0A= + "lwupc $4, dval1 \n\t"=0A= + fp_assert ($4, $5)=0A= + "lwu $5, dval2 \n\t"=0A= + "lwupc $4, dval2 \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 4 \n\t" /* Test LLD */=0A= + "ld $5, dval3 \n\t"=0A= + "dla $3, dval4 \n\t"=0A= + "lld $4, -248($3) \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 5 \n\t" /* Test SCD */=0A= + "lld $4, -248($3) \n\t"=0A= + "dli $4, 0xafaf \n\t"=0A= + "scd $4, -248($3) \n\t"=0A= + "ld $5, dval3 \n\t"=0A= + "dli $4, 0xafaf \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "Lend3: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r" (err) /* outputs */=0A= + : /* inputs */=0A= + : "$3", "$4", "$5", "$6", "$7", "$11" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +int=0A= +test_r6 (void)=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + "dval_1: .word 0xabcd1234 \n\t"=0A= + "dval_2: .word 0x1234eeff \n\t"=0A= + ".fill 248,1,0 \n\t"=0A= + "dval_3: .word 0x55555555 \n\t"=0A= + ".fill 260,1,0 \n\t"=0A= + "dval_4: .word 0xaaaaaaaa \n\t"=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" /* ADDIUPC */=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 8 \n\t"=0A= + "addiupc $5, 4 \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 2 \n\t" /* AUIPC */=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 8 \n\t"=0A= + "aui $4, $4, 8 \n\t"=0A= + "auipc $5, 8 \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 3 \n\t" /* ALUIPC */=0A= + "jal GetPC_2 \n\t"=0A= + "nop \n\t"=0A= + "addiu $4, $6, 16 \n\t"=0A= + "aui $4, $4, 8 \n\t"=0A= + "li $7, 0xffff0000 \n\t"=0A= + "and $4, $4, $7 \n\t"=0A= + "aluipc $5, 8 \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 4 \n\t" /* LWPC */=0A= + "lw $5, dval_1 \n\t"=0A= + "lwpc $4, dval_1 \n\t"=0A= + fp_assert ($4, $5)=0A= + "lw $5, dval_2 \n\t"=0A= + "lwpc $4, dval_2 \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= +/* Testing LL follows.=0A= + * NOTE: May be redundant because SC already contains LL in its test. */= =0A= + "li $11, 5 \n\t"=0A= + "lw $5, dval_2 \n\t"=0A= + "dla $3, dval_3 \n\t"=0A= + "ll $4, -252($3) \n\t"=0A= + fp_assert ($4, $5)=0A= +=0A= + "li $11, 6 \n\t" /* LL-SC sequence */=0A= + "ll $4, -252($3) \n\t"=0A= + "li $4, 0xafaf \n\t"=0A= + "sc $4, -252($3) \n\t"=0A= + "lw $5, dval_2 \n\t"=0A= + "li $4, 0xafaf \n\t"=0A= + fp_assert ($4, $5)=0A= + "b Lend4 \n\t"=0A= + "nop \n\t"=0A= + "GetPC_2: \n\t"=0A= + "move $6, $31 \n\t"=0A= + "jr $31 \n\t"=0A= + "Lend4: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) /* outputs */=0A= + : /* inputs */=0A= + : "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",=0A= + "$11", "$31" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +/* For fpu-branching testing, bc1eq/eqz are enough. */=0A= +=0A= +int=0A= +test_r6_fpu (void)=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= +/* Test qNaN format is 754-2008 */=0A= + "li $11, 1 \n\t"=0A= + "li $4, 0x0 \n\t"=0A= + "li $5, 0x0 \n\t"=0A= + "li $6, 0x7fc00000 \n\t"=0A= + "mtc1 $4, $f2 \n\t"=0A= + "mtc1 $5, $f4 \n\t"=0A= + "div.s $f6, $f2, $f4 \n\t"=0A= + "mfc1 $8, $f6 \n\t"=0A= + fp_assert ($6, $8)=0A= +=0A= + "li $11, 2 \n\t" /* bc1eqz */=0A= + "li $10, 0x01 \n\t"=0A= + "mtc1 $10, $f2 \n\t"=0A= + "mtc1 $0, $f4 \n\t"=0A= + "bc1eqz $f2, 58f \n\t"=0A= + "nop \n\t"=0A= + "bc1eqz $f4, L62 \n\t"=0A= + "nop \n\t"=0A= + "b 58f \n\t"=0A= + "nop \n\t"=0A= +"L62: \n\t"=0A= + "li $11, 3 \n\t" /* bc1nez */=0A= + "bc1nez $f4, 58f \n\t"=0A= + "nop \n\t"=0A= + "bc1nez $f2, Lend8 \n\t"=0A= + "nop \n\t"=0A= + "b 58f \n\t"=0A= + "nop \n\t"=0A= +"Lend8: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) /* outputs */=0A= + : /* inputs */=0A= + : "$4", "$5", "$6", "$8", "$10", "$11", "$31",=0A= + "$f2", "$f4", "$f6" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +/* R6 specific tests for mips64 (64-bit). */=0A= +=0A= +int=0A= +test_r6_llsc_dp (void)=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + ".align 16 \n\t"=0A= + "test_data: \n\t"=0A= + ".word 0xaaaaaaaa \n\t"=0A= + ".word 0xbbbbbbbb \n\t"=0A= + ".word 0xcccccccc \n\t"=0A= + ".word 0xdddddddd \n\t"=0A= + ".align 16 \n\t"=0A= + "end_check: \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0x1 \n\t"=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" /* LLWP */= =0A= + "llwp $2, $3, test_data \n\t"=0A= + checkpair_dword ($2, $3, test_data, end_check)=0A= + "sll $2, $2, 1 \n\t"=0A= + "srl $3, $3, 1 \n\t"=0A= + "move $s0, $2 \n\t"=0A= + "scwp $2, $3, test_data \n\t"=0A= + check32 ($2, 1)=0A= + checkpair_dword ($s0, $3, test_data, end_check)=0A= + /* Test SCWP, done */=0A= + "li $11, 2 \n\t"=0A= + "li $11, 3 \n\t" /* LLDP */= =0A= + "lldp $2, $3, test_data \n\t"=0A= + checkpair_qword ($2, $3, test_data, end_check)=0A= + "dsll $2, $2, 1 \n\t"=0A= + "dsrl $3, $3, 1 \n\t"=0A= + "move $s0, $2 \n\t"=0A= + "scdp $2, $3, test_data \n\t"=0A= + check32 ($2, 1)=0A= + checkpair_qword ($s0, $3, test_data, end_check)=0A= + "li $11, 4 \n\t" /* SCDP done= */=0A= + "Lend5: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) /* outputs */=0A= + : /* inputs */=0A= + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11",=0A= + "$31", "$s0" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +/* R6 specific tests for mips32 (32-bit). */=0A= +=0A= +int=0A= +test_r6_llsc_wp (void)=0A= +{=0A= + volatile int err =3D 0;=0A= +=0A= + asm (=0A= + ".set push \n\t"=0A= + ".set noreorder \n\t"=0A= + ".data \n\t"=0A= + ".align 8 \n\t"=0A= + "test_data_2: \n\t"=0A= + ".word 0xaaaaaaaa \n\t"=0A= + ".word 0xbbbbbbbb \n\t"=0A= + ".align 8 \n\t"=0A= + "end_check_2: \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0 \n\t"=0A= + ".byte 0x1 \n\t"=0A= + ".text \n\t"=0A= + "li $11, 1 \n\t" /* Test LLWP= */=0A= + "llwp $2, $3, test_data_2 \n\t"=0A= + checkpair_dword ($2, $3, test_data_2, end_check_2)=0A= + "sll $2, $2, 1 \n\t"=0A= + "srl $3, $3, 1 \n\t"=0A= + "move $s0, $2 \n\t"=0A= + "scwp $2, $3, test_data_2 \n\t"=0A= + check32 ($2, 1)=0A= + checkpair_dword ($s0, $3, test_data_2, end_check_2)=0A= +/* Test SCWP, done. */=0A= + "li $11, 2 \n\t"=0A= + "Lend6: \n\t"=0A= + "li $11, 0 \n\t"=0A= + "58: \n\t"=0A= + "move %[err], $11 \n\t"=0A= + ".set pop \n\t"=0A= + : [err] "+r"(err) /* outputs */=0A= + : /* inputs */=0A= + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",=0A= + "$11", "$31", "$s0" /* clobbers */=0A= + );=0A= +=0A= + return err;=0A= +}=0A= +=0A= +/* Any test_r6_* function returns non-zero =3D> failure. */=0A= +#define EXPECT(X) if ((X)) abort ();=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + EXPECT (test_r6_branch ());=0A= +=0A= + EXPECT (test_r6_forbidden ());=0A= +=0A= + EXPECT (test_r6_64 ());=0A= +=0A= + EXPECT (test_r6 ());=0A= +=0A= + EXPECT (test_r6_fpu ());=0A= +=0A= + EXPECT (test_r6_llsc_dp ());=0A= +=0A= + EXPECT (test_r6_llsc_wp ());=0A= +=0A= + return 0;=0A= +}=0A= diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.exp b/gdb/testsuite/gdb.arch= /mips-64-r6.exp=0A= new file mode 100644=0A= index 00000000000..5f74b472edf=0A= --- /dev/null=0A= +++ b/gdb/testsuite/gdb.arch/mips-64-r6.exp=0A= @@ -0,0 +1,76 @@=0A= +# Copyright (C) 2023-2024 Free Software Foundation, Inc.=0A= +=0A= +# This program is free software; you can redistribute it and/or modify=0A= +# it under the terms of the GNU General Public License as published by=0A= +# the Free Software Foundation; either version 3 of the License, or=0A= +# (at your option) any later version.=0A= +#=0A= +# This program is distributed in the hope that it will be useful,=0A= +# but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= +# GNU General Public License for more details.=0A= +#=0A= +# You should have received a copy of the GNU General Public License=0A= +# along with this program; if not, see .=0A= +=0A= +################################################################=0A= +################## MIPS Release 6 patch tests ##################=0A= +################################################################=0A= +=0A= +# Send 'si' to gdb until inferior exits.=0A= +proc stepi {} {=0A= + global gdb_prompt=0A= + set timeout [get_largest_timeout]=0A= + set start [timestamp]=0A= + while { [timestamp] - $start < 3*$timeout } {=0A= + gdb_test_multiple "stepi" "" {=0A= + -re ".*exited normally.*" {=0A= + pass "success"=0A= + return=0A= + }=0A= + -re ".*The program is not being run.*" {=0A= + fail "failure"=0A= + return=0A= + }=0A= + -re ".*Breakpoint.*test_.*$gdb_prompt $" {=0A= + }=0A= + -re "$gdb_prompt.*" {=0A= + }=0A= + }=0A= + }=0A= + fail "test failed"=0A= + return=0A= +}=0A= +=0A= +require {istarget "*mips*"}=0A= +=0A= +set testfile "mips-64-r6"=0A= +set srcfile ${testfile}.c=0A= +set binfile ${objdir}/${subdir}/${testfile}=0A= +=0A= +if {[prepare_for_testing "failed to prepare" "${binfile}" "${srcfile}" {de= bug nowarnings}]} {=0A= + untested "failed to prepare"=0A= + return=0A= +}=0A= +=0A= +# Native needs run.=0A= +if { ![runto_main] } {=0A= + untested "couldn't run to main"=0A= + return=0A= +}=0A= +=0A= +set tests ""=0A= +foreach n [list "r6_branch" "r6_forbidden" "r6_64" "r6" "r6_fpu" "r6_llsc_= dp" "r6_llsc_wp"] {=0A= + lappend tests "test_$n"=0A= +}=0A= +=0A= +# Put breakpoint on each test-function=0A= +foreach func $tests {=0A= + if {![gdb_breakpoint "$func"]} {=0A= + untested "couldn't put breakpoint to $func"=0A= + return=0A= + }=0A= +}=0A= +=0A= +# Step through the binary=0A= +stepi=0A= -- =0A= 2.34.1=0A= =0A= =0A= =0A= =0A= =0A= Kevin, many thanks for your suggestions.=