From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3866 invoked by alias); 8 Jan 2015 10:01:56 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 3857 invoked by uid 89); 8 Jan 2015 10:01:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_05,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mga14.intel.com Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Jan 2015 10:01:54 +0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 08 Jan 2015 01:56:57 -0800 X-ExtLoop1: 1 Received: from irsmsx104.ger.corp.intel.com ([163.33.3.159]) by FMSMGA003.fm.intel.com with ESMTP; 08 Jan 2015 01:49:15 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.195]) by IRSMSX104.ger.corp.intel.com ([169.254.5.209]) with mapi id 14.03.0195.001; Thu, 8 Jan 2015 10:01:45 +0000 From: "Sturm, Michael" To: Joel Brobecker , Andreas Arnez CC: "palves@redhat.com" , "eliz@gnu.org" , "mark.kettenis@xs4all.nl" , "Tedeschi, Walfred" , "gdb-patches@sourceware.org" Subject: RE: [PATCH V5 2/3] Add AVX512 register support to gdbserver. Date: Thu, 08 Jan 2015 10:01:00 -0000 Message-ID: References: <1398258160-9070-1-git-send-email-michael.sturm@intel.com> <1398258160-9070-3-git-send-email-michael.sturm@intel.com> <87ppcgrh0o.fsf@br87z6lw.de.ibm.com> <20141213134146.GE5457@adacore.com> In-Reply-To: <20141213134146.GE5457@adacore.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-01/txt/msg00165.txt.bz2 Hello All, Happy New Year to everyone! Sorry for the late reply! Yes, the proposed change is correct. Thanks a lot= for catching this bug! Regards, Michael -----Original Message----- From: Joel Brobecker [mailto:brobecker@adacore.com]=20 Sent: Saturday, December 13, 2014 2:42 PM To: Andreas Arnez Cc: Sturm, Michael; palves@redhat.com; eliz@gnu.org; mark.kettenis@xs4all.n= l; Tedeschi, Walfred; gdb-patches@sourceware.org Subject: Re: [PATCH V5 2/3] Add AVX512 register support to gdbserver. > While building GDB I encountered a gcc warning (array subscript above=20 > array bounds) and tracked it down to the patch below. Thanks! > On Wed, Apr 23 2014, Michael Sturm wrote: >=20 > > # Linux object files. This is so we don't have to repeat diff=20 > > --git a/gdb/gdbserver/i387-fp.c b/gdb/gdbserver/i387-fp.c index=20 > > e655f74..c2d0bdf 100644 > > --- a/gdb/gdbserver/i387-fp.c > > +++ b/gdb/gdbserver/i387-fp.c > > @@ -22,6 +22,11 @@ > >=20=20 > > static const int num_mpx_bnd_registers =3D 4; static const int=20 > > num_mpx_cfg_registers =3D 2; > > +static const int num_avx512_k_registers =3D 8; static const int=20 > > +num_avx512_zmmh_low_registers =3D 16; static const int=20 > > +num_avx512_zmmh_high_registers =3D 16; static const int=20 > > +num_avx512_ymmh_registers =3D 16; static const int=20 > > +num_avx512_xmm_registers =3D 16; > >=20=20 > > /* Note: These functions preserve the reserved bits in control registe= rs. > > However, gdbserver promptly throws away that information. */ @@=20 > > -120,6 +125,17 @@ struct i387_xsave { > > /* Space for 2 MPX configuration registers of 64 bits > > plus reserved space. */ > > unsigned char mpx_cfg_space[16]; > > + > > + unsigned char reserved5[48]; > > + > > + /* Space for 8 OpMask register values of 64 bits. */ unsigned=20 > > + char k_space[64]; > > + > > + /* Space for 16 256-bit zmm0-15. */ unsigned char=20 > > + zmmh_low_space[512]; > > + > > + /* Space for 16 512-bit zmm16-31 values. */ unsigned char=20 > > + zmmh_high_space[1024]; > > }; > > > > [...] > > + > > + /* Check if any of ZMM16H-ZMM31H registers are changed. */ if=20 > > + ((x86_xcr0 & I386_XSTATE_ZMM)) > > + { > > + int zmm16h_regnum =3D find_regno (regcache->tdesc, "zmm16h"); > > + > > + for (i =3D 0; i < num_avx512_zmmh_high_registers; i++) > > + { > > + collect_register (regcache, i + zmm16h_regnum, raw); > > + p =3D ((char *) &fp->zmmh_low_space[0]) + 32 + i * 64; > ^^^^^^^^^^^^^^ Should this really mean=20 > 'zmm_high_space'? >=20 > > + if (memcmp (raw, p, 32) !=3D 0) >=20 > The warning occurs for this memcmp(). Based on the comments in "struct i387_xsave", I think you are right! Michael and/or Pedro, can anyone confirm, please? Thank you, -- Joel Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052