From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9282 invoked by alias); 5 Dec 2016 12:25:50 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 9271 invoked by uid 89); 5 Dec 2016 12:25:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=BAYES_50,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=H*u:sk:Microso, HMime-version:1.0, H*UA:sk:Microso, HContent-type:plain X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Dec 2016 12:25:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88AEF15AB; Mon, 5 Dec 2016 04:25:37 -0800 (PST) Received: from [10.45.32.207] (e105284-mac.manchester.arm.com [10.45.32.207]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6B3E3F445 for ; Mon, 5 Dec 2016 04:25:36 -0800 (PST) User-Agent: Microsoft-MacOutlook/14.7.0.161029 Date: Mon, 05 Dec 2016 12:25:00 -0000 Subject: [PATCH 0/8] AARCH64 SVE: Initial SVE support From: Alan Hayward To: Message-ID: Mime-version: 1.0 Content-type: text/plain; charset="UTF-8" Content-transfer-encoding: 7bit X-SW-Source: 2016-12/txt/msg00131.txt.bz2 Hi, I'd like to submit GDB and gdbserver support for ARM's Scalable Vector Extension (SVE). For more details about the extension itself, please see Nigel's blog post at: https://community.arm.com/groups/processors/blog/2016/08/22/technology-upda te-the-scalable-vector-extension-sve-for-the-armv8-a-architecture Francesco has also written a white paper about programming for SVE, with some worked examples: http://developer.arm.com/hpc/a-sneak-peek-into-sve-and-vla-programming In order to support SVE, GDB needs to be able to handle registers which may change size at any time whilst the debugged program is running. The target architecture descriptions (patch 5) contain a minimum size for each variable register. GDB (patch 7) and gdbserver (patch 8) must then scale these registers using the current VG for the target (obtained using ptrace). This also requires increasing the maximum register size to 256 bytes (patch 1). For these sets of patches to work, Linux Kernel support also needs adding, which is currently under review here: http://archive.arm.linux.org.uk/lurker/message/20161125.193848.bec98fed.en. html Without kernel support, the code will safely fall back to non-SVE Aarch64. These patches assume the vector length the same across a process, which is consistant with the current Kernel implementation. Once support is added to the kernel for independent vector lengths per thread, then further patches will be required to allow a different target descriptor for each thread. Thanks, Alan Hayward.