From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13047 invoked by alias); 9 Oct 2018 17:29:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 12976 invoked by uid 89); 9 Oct 2018 17:29:51 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=blackmore, Blackmore X-HELO: resqmta-po-10v.sys.comcast.net Received: from resqmta-po-10v.sys.comcast.net (HELO resqmta-po-10v.sys.comcast.net) (96.114.154.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 Oct 2018 17:29:49 +0000 Received: from resomta-po-04v.sys.comcast.net ([96.114.154.228]) by resqmta-po-10v.sys.comcast.net with ESMTP id 9vEkgWbU0csma9vpMguLKP; Tue, 09 Oct 2018 17:29:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=comcast.net; s=q20161114; t=1539106188; bh=jBduup2EgEocCztOGDSLT+EDMAV7iye5ZLWcbIUy7yM=; h=Received:Received:Content-Type:Mime-Version:Subject:From:Date: Message-Id:To; b=G5Iz/19+XNs/bHZm1TkcEVYYq2lohJRrS/WOzLyP3SeR5loya4rbmo8KCQh8QXy2u +djwzOP99BXxZugPl9ORC5rKvC6Z6sx1rjj8u0HWhlhaXKw/BZRNegC8wrCB93bSQQ 6sCkzKlzxn5v2iOJpJS7vNBFmPadYcVr6+3B66Vh6XS5f0qvk3GKwjYXGK1hbW4AOb qtJBbO4FhjLxEAKG8FKKCQpfXi6ZpRr494dgqLJZXkVajs/CAS2EFyX4YjWktic/8Z HHYuw6JvmolNGo3p5YUaEdy46cJwhUY3xt3lHi2O1uywYEpW5p+Qv4wFHnx2wQTU2n G5gpOjG9uyJHw== Received: from [192.168.10.125] ([73.60.223.101]) by resomta-po-04v.sys.comcast.net with ESMTPSA id 9vpLgzKzD15A69vpLgs9Zb; Tue, 09 Oct 2018 17:29:48 +0000 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default From: Paul Koning In-Reply-To: <5bd138ad-4d1d-254c-9d35-1873b2d8f5f4@embecosm.com> Date: Tue, 09 Oct 2018 17:29:00 -0000 Cc: Joel Brobecker , Pedro Alves , Andrew Burgess , gdb-patches@sourceware.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20180917103409.GJ5952@embecosm.com> <77978648-c391-0011-6c03-c7fd38429914@embecosm.com> <20181003223703.GA22933@adacore.com> <20181008095839.GC5952@embecosm.com> <4c4c1369-0f5c-549a-ed82-51563c5e6dd6@redhat.com> <20181008142533.GA2993@adacore.com> <5019D845-3AEB-4287-A8BD-D9F96F5755B7@comcast.net> <20181008145132.GB2993@adacore.com> <5bd138ad-4d1d-254c-9d35-1873b2d8f5f4@embecosm.com> To: Craig Blackmore X-SW-Source: 2018-10/txt/msg00220.txt.bz2 > On Oct 9, 2018, at 1:20 PM, Craig Blackmore wrote: >=20 >=20 >=20 > On 08/10/18 15:51, Joel Brobecker wrote: >>>> I think MIPS is one. The documentation is not entirely clear but >>>> that's what I remember from using it. >>> x86 is another. But my question is -- do we know of any RISC-V >>> implementation that triggers after the write, given that the spec >>> says it should trigger before the write. > I don't know of any RISC-V implementations that trigger after the write. > The debug spec has 'suggested breakpoint timings' but the triggers are > allowed to fire at whatever point is most convenient for the implementati= on. I missed that the question was specific to RISC-V. If the spec says that timing is up to the implementation, that seems to mea= n GDB can't rely on the break occurring before the write -- the fact that c= urrent implementations do so isn't sufficient if later implementation are a= llowed to differ. I assume GDB cares which it is, which suggests that the implementation has = to tell GDB which flavor of write watchpoint it has. paul