From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9125 invoked by alias); 12 Feb 2020 23:28:53 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 9117 invoked by uid 89); 12 Feb 2020 23:28:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-29.5 required=5.0 tests=AWL,BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS,USER_IN_DEF_SPF_WL autolearn=ham version=3.3.1 spammy=forgive X-HELO: mail-ot1-f67.google.com Received: from mail-ot1-f67.google.com (HELO mail-ot1-f67.google.com) (209.85.210.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Feb 2020 23:28:49 +0000 Received: by mail-ot1-f67.google.com with SMTP id d3so3763101otp.4 for ; Wed, 12 Feb 2020 15:28:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=tQFPinOfR7YQFx+TdzSdlK7B3GDub3847yomzjf9BfU=; b=Cit/dcn/3gteWacbXs+ffvEimnD2KHT6WMSnwKo3z6qCQZxZG16yVzJHYRtmT8D9aP xj6+TjH0QKGUKZ3eNrY4Kf2+1qDHuDBkgpdB8GonaFM7S7Rh4gPA22ODO6XWSPwRN6r4 hr+t+BHoVjIGVBO5v0adLYWgR79+kDHZfRYaciNmlBnTOgVFJN2Z1cQqJLIsO7TPc65e zM4SbyS/5ZTVsF+b37Iftp0yawBvqoZjsYpYa/ruLfUouRkP7GZaq2WjqIrguaDo8JzK Na7y7Ejpo8vZVZ80CFldhAAk6nmO2JySgdmaPccxRGiSXdJHfZHLQqeNeeEieGu+DlrM AvKg== MIME-Version: 1.0 References: <20200211225503.32992-1-cbiesinger@google.com> <57C0F31A-7085-4722-93B6-062DF7A10E58@arm.com> <96a09009-a9c9-aad2-5a83-e08f7e8dcb68@gmx.com> In-Reply-To: <96a09009-a9c9-aad2-5a83-e08f7e8dcb68@gmx.com> From: "Christian Biesinger via gdb-patches" Reply-To: Christian Biesinger Date: Wed, 12 Feb 2020 23:28:00 -0000 Message-ID: Subject: Re: [PATCH] Fix arm-netbsd build error To: Kamil Rytarowski Cc: Alan Hayward , gdb-patches , nd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00477.txt.bz2 Thanks, Kamil! Please forgive the stupid question, but is SIMD in this context the same as IWMMXT? Christian On Wed, Feb 12, 2020 at 11:16 AM Kamil Rytarowski wrote: > > On 12.02.2020 18:09, Kamil Rytarowski wrote: > > On 12.02.2020 17:28, Christian Biesinger wrote: > >> On Wed, Feb 12, 2020 at 7:29 AM Alan Hayward wr= ote: > >>> > >>> > >>> > >>>> On 11 Feb 2020, at 23:34, Christian Biesinger via gdb-patches wrote: > >>>> > >>>> On Tue, Feb 11, 2020 at 4:55 PM Christian Biesinger > >>>> wrote: > >>>>> > >>>>> The floating point register interface has changed to this: > >>>>> https://github.com/NetBSD/src/blob/trunk/sys/arch/arm/include/reg.h > >>>>> > >>>>> It now uses VFP instead of FPA registers. This patch updates > >>>>> arm-nbsd-nat.c accordingly. > >>>>> > >>>>> Tested by compiling on arm-netbsd on qemu. For actually testing, th= ere > >>>>> seems to be something missing as "info registers" only shows FPA > >>>>> registers and no VFP ones. I am still investigating why this is; > >>>>> please let me know if you know. However, I think this is still good > >>>>> to check in as-is. > >>>> > >>>> Hm... this is perhaps because arm_netbsd_nat_target does not impleme= nt > >>>> read_description; if it returned arm_read_description > >>>> (ARM_FP_TYPE_VFPV2) this may work? > >>>> > >>> > >>> Yes, looks like netbsd isn=E2=80=99t using any target description fun= ctionality. > >>> > >>> I suspect the code is getting into arm_gdbarch_init() with a null tde= sc, > >>> and then using the AUTO setting. But that=E2=80=99s just a guess. > >>> > >>> Implementing read_description as you suggest should help. However, > >>> read_description should probably do HWCAP checking similar to the > >>> arm_linux_nat_target and arm_fbsd_nat_target versions. > >>> > >>> Without that, I=E2=80=99d worry that your patch below might start wri= ting off the > >>> end of the regcache that had been allocated for a fewer number of reg= isters. > >> > >> Hm... well, I've probably spent entirely too much time on this > >> already, but just in case there's an easy fix -- Kamil, does NetBSD > >> provide an API similar to Linux's HWCAP API that would let me check > >> which VFP version the current CPU is using? It seems AUXV does not > >> contain HWCAP data on NetBSD, unlike Linux/FreeBSD, though I may be > >> missing something. > >> > >> (Compare arm_fbsd_read_description_auxv / > >> arm_linux_nat_target::read_description) > >> > >> Christian > >> > > > > Thank you for your work. > > > > HWCAP in auxv is not supported (although there is a stub for it). > > > > Here is a complete algorithm to detect FPU on ARM 32-bit. > > > > http://netbsd.org/~kamil/arm-fpu.c > > > > Here is another example with SIMD: > > http://cvsweb.netbsd.org/bsdweb.cgi/xsrc/external/mit/pixman/dist/pixman/= pixman-arm.c.diff?r1=3D1.1&r2=3D1.2&f=3Dh > > >>> > >>>>> > >>>>> gdb/ChangeLog: > >>>>> > >>>>> 2020-02-11 Christian Biesinger > >>>>> > >>>>> * arm-nbsd-nat.c (arm_supply_fparegset): Rename to... > >>>>> (arm_supply_vfpregset): ...this, and update to use VFP regis= ters. > >>>>> (fetch_fp_register): Update. > >>>>> (fetch_fp_regs): Update. > >>>>> (store_fp_register): Update. > >>>>> (store_fp_regs): Update. > >>>>> (fetch_elfcore_registers): Update. > >>>>> --- > >>>>> gdb/arm-nbsd-nat.c | 80 ++++++++++++++++++++-----------------------= --- > >>>>> 1 file changed, 34 insertions(+), 46 deletions(-) > >>>>> > >>>>> diff --git a/gdb/arm-nbsd-nat.c b/gdb/arm-nbsd-nat.c > >>>>> index 11afc289c3..8027f54dfe 100644 > >>>>> --- a/gdb/arm-nbsd-nat.c > >>>>> +++ b/gdb/arm-nbsd-nat.c > >>>>> @@ -65,15 +65,13 @@ arm_supply_gregset (struct regcache *regcache, = struct reg *gregset) > >>>>> } > >>>>> > >>>>> static void > >>>>> -arm_supply_fparegset (struct regcache *regcache, struct fpreg *fpa= regset) > >>>>> +arm_supply_vfpregset (struct regcache *regcache, struct fpreg *fpr= egset) > >>>>> { > >>>>> - int regno; > >>>>> - > >>>>> - for (regno =3D ARM_F0_REGNUM; regno <=3D ARM_F7_REGNUM; regno++) > >>>>> - regcache->raw_supply (regno, > >>>>> - (char *) &fparegset->fpr[regno - ARM_F0_R= EGNUM]); > >>>>> + struct vfpreg &vfp =3D fpregset->fpr_vfp; > >>>>> + for (int regno =3D ARM_D0_REGNUM; regno <=3D ARM_D31_REGNUM; reg= no++) > >>>>> + regcache->raw_supply (regno, (char *) &vfp.vfp_regs[regno - AR= M_D0_REGNUM]); > >>>>> > >>>>> - regcache->raw_supply (ARM_FPS_REGNUM, (char *) &fparegset->fpr_f= psr); > >>>>> + regcache->raw_supply (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fpscr); > >>>>> } > >>>>> > >>>>> static void > >>>>> @@ -147,10 +145,10 @@ static void > >>>>> fetch_fp_register (struct regcache *regcache, int regno) > >>>>> { > >>>>> struct fpreg inferior_fp_registers; > >>>>> - int ret; > >>>>> + int ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), > >>>>> + (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> > >>>>> - ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), > >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> + struct vfpreg &vfp =3D inferior_fp_registers.fpr_vfp; > >>>>> > >>>>> if (ret < 0) > >>>>> { > >>>>> @@ -158,18 +156,15 @@ fetch_fp_register (struct regcache *regcache,= int regno) > >>>>> return; > >>>>> } > >>>>> > >>>>> - switch (regno) > >>>>> + if (regno =3D=3D ARM_FPSCR_REGNUM) > >>>>> + regcache->raw_supply (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fpsc= r); > >>>>> + else if (regno >=3D ARM_D0_REGNUM && regno <=3D ARM_D31_REGNUM) > >>>>> { > >>>>> - case ARM_FPS_REGNUM: > >>>>> - regcache->raw_supply (ARM_FPS_REGNUM, > >>>>> - (char *) &inferior_fp_registers.fpr_fps= r); > >>>>> - break; > >>>>> - > >>>>> - default: > >>>>> - regcache->raw_supply > >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_= REGNUM]); > >>>>> - break; > >>>>> + regcache->raw_supply (regno, > >>>>> + (char *) &vfp.vfp_regs[regno - ARM_D0_R= EGNUM]); > >>>>> } > >>>>> + else > >>>>> + warning (_("Invalid register number.")); > >>>>> } > >>>>> > >>>>> static void > >>>>> @@ -188,7 +183,7 @@ fetch_fp_regs (struct regcache *regcache) > >>>>> return; > >>>>> } > >>>>> > >>>>> - arm_supply_fparegset (regcache, &inferior_fp_registers); > >>>>> + arm_supply_vfpregset (regcache, &inferior_fp_registers); > >>>>> } > >>>>> > >>>>> void > >>>>> @@ -327,10 +322,9 @@ static void > >>>>> store_fp_register (const struct regcache *regcache, int regno) > >>>>> { > >>>>> struct fpreg inferior_fp_registers; > >>>>> - int ret; > >>>>> - > >>>>> - ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), > >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> + int ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), > >>>>> + (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> + struct vfpreg &vfp =3D inferior_fp_registers.fpr_vfp; > >>>>> > >>>>> if (ret < 0) > >>>>> { > >>>>> @@ -338,18 +332,15 @@ store_fp_register (const struct regcache *reg= cache, int regno) > >>>>> return; > >>>>> } > >>>>> > >>>>> - switch (regno) > >>>>> + if (regno =3D=3D ARM_FPSCR_REGNUM) > >>>>> + regcache->raw_collect (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fps= cr); > >>>>> + else if (regno >=3D ARM_D0_REGNUM && regno <=3D ARM_D31_REGNUM) > >>>>> { > >>>>> - case ARM_FPS_REGNUM: > >>>>> - regcache->raw_collect (ARM_FPS_REGNUM, > >>>>> - (char *) &inferior_fp_registers.fpr_fp= sr); > >>>>> - break; > >>>>> - > >>>>> - default: > >>>>> - regcache->raw_collect > >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_= REGNUM]); > >>>>> - break; > >>>>> + regcache->raw_collect (regno, > >>>>> + (char *) &vfp.vfp_regs[regno - ARM_D0_= REGNUM]); > >>>>> } > >>>>> + else > >>>>> + warning (_("Invalid register number.")); > >>>>> > >>>>> ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), > >>>>> (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> @@ -361,20 +352,17 @@ store_fp_register (const struct regcache *reg= cache, int regno) > >>>>> static void > >>>>> store_fp_regs (const struct regcache *regcache) > >>>>> { > >>>>> - struct fpreg inferior_fp_registers; > >>>>> - int ret; > >>>>> - int regno; > >>>>> + struct fpreg fpregs; > >>>>> > >>>>> - > >>>>> - for (regno =3D ARM_F0_REGNUM; regno <=3D ARM_F7_REGNUM; regno++) > >>>>> + for (int regno =3D ARM_D0_REGNUM; regno <=3D ARM_D31_REGNUM; reg= no++) > >>>>> regcache->raw_collect > >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_R= EGNUM]); > >>>>> + (regno, (char *) &fpregs.fpr_vfp.vfp_regs[regno - ARM_D0_REG= NUM]); > >>>>> > >>>>> - regcache->raw_collect (ARM_FPS_REGNUM, > >>>>> - (char *) &inferior_fp_registers.fpr_fpsr); > >>>>> + regcache->raw_collect (ARM_FPSCR_REGNUM, > >>>>> + (char *) &fpregs.fpr_vfp.vfp_fpscr); > >>>>> > >>>>> - ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), > >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); > >>>>> + int ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), > >>>>> + (PTRACE_TYPE_ARG3) &fpregs, 0); > >>>>> > >>>>> if (ret < 0) > >>>>> warning (_("unable to store floating-point registers")); > >>>>> @@ -427,7 +415,7 @@ fetch_elfcore_registers (struct regcache *regca= che, > >>>>> /* The memcpy may be unnecessary, but we can't really be s= ure > >>>>> of the alignment of the data in the core file. */ > >>>>> memcpy (&fparegset, core_reg_sect, sizeof (fparegset)); > >>>>> - arm_supply_fparegset (regcache, &fparegset); > >>>>> + arm_supply_vfpregset (regcache, &fparegset); > >>>>> } > >>>>> break; > >>>>> > >>>>> -- > >>>>> 2.25.0.225.g125e21ebc7-goog > >>>>> > >>> > > > > > >