From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4061 invoked by alias); 2 Sep 2014 14:55:39 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 4050 invoked by uid 89); 2 Sep 2014 14:55:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ie0-f180.google.com Received: from mail-ie0-f180.google.com (HELO mail-ie0-f180.google.com) (209.85.223.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 02 Sep 2014 14:55:37 +0000 Received: by mail-ie0-f180.google.com with SMTP id rl12so7539431iec.25 for ; Tue, 02 Sep 2014 07:55:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=UGxzXq6SgrvfEi7RS073+lx5ApJ0L1alIe9vXS9RDhc=; b=fvtXTgpaLkhco8Oq7XpZmqz18hgey1jczXY+YV8Ar5eIKDOTvD/8axhGt50lIqBpbF OeWkkGXdbbRjlhBX2l94MWvXHiDAxlwasZvXlFQJsoL3eqjMMgJrQqoEXadLEHgr2ajM 6WEXO2IgrWELLwT5nyP3fafQ9pmrLPsIAomcWmWpsxzc01oKXb5khpxFxuqi68mO+DaO Atgx6heaDpDY8tUOBZkJU/YSAQms90HnM9hRbzETNRKqr+iuYv3UReyVGC3B/LXqGbvZ oSDew7P2MeH2NZHcXzXD5DczWnKTP3nlKUoN745HtJlymqNR8LfrgiOmLH+u9znFFAto xE6Q== X-Gm-Message-State: ALoCoQnYZ5s1IptZhoiaMnb8JIEfiEcA3kPokI1FhZzSLxMrXLWqr5smU+pyUJkVbRBvvNLyv3qQ MIME-Version: 1.0 X-Received: by 10.42.137.194 with SMTP id z2mr1478804ict.85.1409669735128; Tue, 02 Sep 2014 07:55:35 -0700 (PDT) Received: by 10.64.142.116 with HTTP; Tue, 2 Sep 2014 07:55:35 -0700 (PDT) In-Reply-To: <1409223378-13707-1-git-send-email-omair.javaid@linaro.org> References: <53FDAE64.1070407@redhat.com> <1409223378-13707-1-git-send-email-omair.javaid@linaro.org> Date: Tue, 02 Sep 2014 14:55:00 -0000 Message-ID: Subject: Re: [PATCH v3 2/6] Implement support for recording thumb2 ASIMD struct ld/st insns From: Will Newton To: Omair Javaid Cc: "gdb-patches@sourceware.org" Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg00058.txt.bz2 On 28 August 2014 11:56, Omair Javaid wrote: > gdb: > > 2014-08-13 Omair Javaid > > * arm-tdep.c (thumb2_record_asimd_struct_ld_st): Add record handler > for advance SIMD struct ld/st insn. > (thumb2_record_decode_insn_handler): Replace stub handler with > thumb2_record_asimd_struct_ld_st. > > --- > gdb/arm-tdep.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 191 insertions(+), 1 deletion(-) This version does not seem to address the issues raised in my previous review e.g. bf_align variable. > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index d659897..a4a7f15 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -13078,6 +13078,196 @@ thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) > return arm_record_asimd_vfp_coproc (thumb2_insn_r); > } > > +/* Record handler for advance SIMD structure load/store instructions. */ > + > +static int > +thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) > +{ > + struct regcache *reg_cache = thumb2_insn_r->regcache; > + uint32_t l_bit, a_bit, b_bits; > + uint32_t record_buf[128], record_buf_mem[128]; > + uint32_t reg_rn, reg_vd, address, f_esize, f_elem; > + uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; > + uint8_t bf_align, f_ebytes; > + > + l_bit = bit (thumb2_insn_r->arm_insn, 21); > + a_bit = bit (thumb2_insn_r->arm_insn, 23); > + b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); > + bf_align = bits (thumb2_insn_r->arm_insn, 4, 5); > + reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); > + reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); > + reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; > + f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); > + f_esize = 8 * f_ebytes; > + f_elem = 8 / f_ebytes; > + > + if (!l_bit) > + { > + ULONGEST u_regval = 0; > + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); > + address = u_regval; > + > + if (!a_bit) > + { > + /* Handle VST1. */ > + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) > + { > + if (b_bits == 0x07) > + bf_regs = 1; > + else if (b_bits == 0x0a) > + bf_regs = 2; > + else if (b_bits == 0x06) > + bf_regs = 3; > + else if (b_bits == 0x02) > + bf_regs = 4; > + else > + bf_regs = 0; > + > + for (index_r = 0; index_r < bf_regs; index_r++) > + { > + for (index_e = 0; index_e < f_elem; index_e++) > + { > + record_buf_mem[index_m++] = f_ebytes; > + record_buf_mem[index_m++] = address; > + address = address + f_ebytes; > + thumb2_insn_r->mem_rec_count += 1; > + } > + } > + } > + /* Handle VST2. */ > + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) > + { > + if (b_bits == 0x09 || b_bits == 0x08) > + bf_regs = 1; > + else if (b_bits == 0x03) > + bf_regs = 2; > + else > + bf_regs = 0; > + > + for (index_r = 0; index_r < bf_regs; index_r++) > + for (index_e = 0; index_e < f_elem; index_e++) > + { > + for (loop_t = 0; loop_t < 2; loop_t++) > + { > + record_buf_mem[index_m++] = f_ebytes; > + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); > + thumb2_insn_r->mem_rec_count += 1; > + } > + address = address + (2 * f_ebytes); > + } > + } > + /* Handle VST3. */ > + else if ((b_bits & 0x0e) == 0x04) > + { > + for (index_e = 0; index_e < f_elem; index_e++) > + { > + for (loop_t = 0; loop_t < 3; loop_t++) > + { > + record_buf_mem[index_m++] = f_ebytes; > + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); > + thumb2_insn_r->mem_rec_count += 1; > + } > + address = address + (3 * f_ebytes); > + } > + } > + /* Handle VST4. */ > + else if (!(b_bits & 0x0e)) > + { > + for (index_e = 0; index_e < f_elem; index_e++) > + { > + for (loop_t = 0; loop_t < 4; loop_t++) > + { > + record_buf_mem[index_m++] = f_ebytes; > + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); > + thumb2_insn_r->mem_rec_count += 1; > + } > + address = address + (4 * f_ebytes); > + } > + } > + } > + else > + { > + uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); > + > + if (bft_size == 0x00) > + f_ebytes = 1; > + else if (bft_size == 0x01) > + f_ebytes = 2; > + else if (bft_size == 0x02) > + f_ebytes = 4; > + else > + f_ebytes = 0; > + > + /* Handle VST1. */ > + if (!(b_bits & 0x0b) || b_bits == 0x08) > + thumb2_insn_r->mem_rec_count = 1; > + /* Handle VST2. */ > + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) > + thumb2_insn_r->mem_rec_count = 2; > + /* Handle VST3. */ > + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) > + thumb2_insn_r->mem_rec_count = 3; > + /* Handle VST4. */ > + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) > + thumb2_insn_r->mem_rec_count = 4; > + > + for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) > + { > + record_buf_mem[index_m] = f_ebytes; > + record_buf_mem[index_m] = address + (index_m * f_ebytes); > + } > + } > + } > + else > + { > + if (!a_bit) > + { > + /* Handle VLD1. */ > + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) > + thumb2_insn_r->reg_rec_count = 1; > + /* Handle VLD2. */ > + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) > + thumb2_insn_r->reg_rec_count = 2; > + /* Handle VLD3. */ > + else if ((b_bits & 0x0e) == 0x04) > + thumb2_insn_r->reg_rec_count = 3; > + /* Handle VLD4. */ > + else if (!(b_bits & 0x0e)) > + thumb2_insn_r->reg_rec_count = 4; > + } > + else > + { > + /* Handle VLD1. */ > + if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) > + thumb2_insn_r->reg_rec_count = 1; > + /* Handle VLD2. */ > + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) > + thumb2_insn_r->reg_rec_count = 2; > + /* Handle VLD3. */ > + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) > + thumb2_insn_r->reg_rec_count = 3; > + /* Handle VLD4. */ > + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) > + thumb2_insn_r->reg_rec_count = 4; > + > + for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) > + record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; > + } > + } > + > + if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) > + { > + record_buf[index_r] = reg_rn; > + thumb2_insn_r->reg_rec_count += 1; > + } > + > + REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, > + record_buf); > + MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, > + record_buf_mem); > + return 0; > +} > + > /* Decodes thumb2 instruction type and invokes its record handler. */ > > static unsigned int > @@ -13140,7 +13330,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) > else if (!((op2 & 0x71) ^ 0x10)) > { > /* Advanced SIMD or structure load/store instructions. */ > - return arm_record_unsupported_insn (thumb2_insn_r); > + return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); > } > else if (!((op2 & 0x67) ^ 0x01)) > { > -- > 1.9.1 > -- Will Newton Toolchain Working Group, Linaro