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Thu, 29 Jan 2026 15:18:54 -0800 (PST) MIME-Version: 1.0 References: <20260129181122.1426596-1-peter.maydell@linaro.org> In-Reply-To: <20260129181122.1426596-1-peter.maydell@linaro.org> From: Luis Date: Thu, 29 Jan 2026 23:13:11 +0000 X-Gm-Features: AZwV_Qibs5AQVuv3o-_RrP3mHTQQRzVD3oEDvxz80yvmLu01_MQzvymq53weLgY Message-ID: Subject: Re: [PATCH] docs: Clarify gdb remote protocol AArch64 SVE and SME handling To: Peter Maydell Cc: gdb-patches@sourceware.org, Thiago Jung Bauermann , Manos Pitsidianakis Content-Type: multipart/alternative; boundary="0000000000008b04d706498f1441" X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org --0000000000008b04d706498f1441 Content-Type: text/plain; charset="UTF-8" On Thu, Jan 29, 2026, 18:11 Peter Maydell wrote: > The documentation of the AArch64 target features for the gdb remote > protocol has some areas where it is unclear about SVE and SME: > > * it doesn't say what to do if the target has only SME > > * it isn't clear about what the org.gnu.gdb.aarch64.sve vector > register size should be when both SME and SVE are present > > Clarify/correct the documentation: > > * org.gnu.gdb.aarch64.sve is effectively "the feature for the z > vector registers", and must be provided even when the target only > implements SME (because the z registers exist in an SME only CPU) > > * the z register size and the 'vg' pseudoregister in > org.gnu.gdb.aarch64.sve follow the architectural "effective SVE > vector length", which might be either the non-streaming SVE vector > length or the streaming SVE vector length > > Reviewed-by: Thiago Jung Bauermann > --- > gdb/doc/gdb.texinfo | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo > index 80f49e21b7e..711a45435ef 100644 > --- a/gdb/doc/gdb.texinfo > +++ b/gdb/doc/gdb.texinfo > @@ -49742,7 +49742,8 @@ Extra registers are allowed in this feature, but > they will not affect > @subsubsection AArch64 SVE registers feature > > The @samp{org.gnu.gdb.aarch64.sve} feature is optional. If present, > -it means the target supports the Scalable Vector Extension and must > contain > +it means the target supports either the Scalable Vector Extension (SVE) or > +the Scalable Matrix Extension (SME) and must contain > the following registers: > > @itemize @minus > @@ -49780,6 +49781,14 @@ vector registers from the > @samp{org.gnu.gdb.aarch64.fpu} feature. > The first 128 bits of the @samp{z} registers overlap the 128 bits of the > @samp{v} registers, so changing one will trigger a change to the other. > > +@samp{vg} represents the size of the @samp{z} registers, and is what > +the Arm architecture defines as the ``Effective SVE vector length''. That > +means that if the target implements SME and is in streaming vector mode, > +it is the streaming vector length. If the target implements only SME and > +not SVE, and is not in streaming vector mode, then @samp{vg} is 2 > +(indicating 128-bit vectors) and the @samp{z} registers match the @samp{v} > +FPU registers. > + > For the types of the @samp{z}, @samp{p} and @samp{ffr} registers, please > check the aarch64-sve.c file. No XML file is available for this feature > because it is dynamically generated based on the current vector length. > @@ -49793,6 +49802,9 @@ aarch64-sve.c file, and should match what is > described in aarch64-fpu.xml. > Extra registers are allowed in this feature, but they will not affect > @value{GDBN}. > > +The @samp{org.gnu.gdb.aarch64.sve} feature is required when the target > also > +reports support for the @samp{org.gnu.gdb.aarch64.sme} feature. > + > @subsubsection AArch64 Pointer Authentication registers feature > > The @samp{org.gnu.gdb.aarch64.pauth} optional feature was introduced so > @@ -49948,6 +49960,10 @@ extensions of the architecture. > Extra registers are allowed in this feature, but they will not affect > @value{GDBN}. > > +Note that a target with only SME but not SVE support must still > +provide the @samp{org.gnu.gdb.aarch64.sve} feature, to expose the > +@samp{z} vector registers. > + > The @samp{org.gnu.gdb.aarch64.sme} feature is required when the target > also > reports support for the @samp{org.gnu.gdb.aarch64.sme2} feature. > > -- > 2.43.0 > Thanks. The documentation update looks OK given the current needs, but I'm not too sure about keeping the SVE feature just for the Z registers. I find that a bit confusing. It might be cleaner to clearly separate SVE and SME features, adding Z registers to a SME feature if needed when SVE is disabled. Or something similar to that. I don't feel comfortable setting this is stone before we have a patch that clarifies how this separation between SVE and SME is achieved. > --0000000000008b04d706498f1441 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Thu, Jan 29, 2026, 18:11 Peter Maydel= l <peter.maydell@linaro.org<= /a>> wrote:
The documentation of= the AArch64 target features for the gdb remote
protocol has some areas where it is unclear about SVE and SME:

=C2=A0* it doesn't say what to do if the target has only SME

=C2=A0* it isn't clear about what the org.gnu.gdb.aarch64.sve vector =C2=A0 =C2=A0register size should be when both SME and SVE are present

Clarify/correct the documentation:

=C2=A0* org.gnu.gdb.aarch64.sve is effectively "the feature for the z<= br> =C2=A0 =C2=A0vector registers", and must be provided even when the tar= get only
=C2=A0 =C2=A0implements SME (because the z registers exist in an SME only C= PU)

=C2=A0* the z register size and the 'vg' pseudoregister in
=C2=A0 =C2=A0org.gnu.gdb.aarch64.sve follow the architectural "effecti= ve SVE
=C2=A0 =C2=A0vector length", which might be either the non-streaming S= VE vector
=C2=A0 =C2=A0length or the streaming SVE vector length

Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org= >
---
=C2=A0gdb/doc/gdb.texinfo | 18 +++++++++++++++++-
=C2=A01 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 80f49e21b7e..711a45435ef 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -49742,7 +49742,8 @@ Extra registers are allowed in this feature, but th= ey will not affect
=C2=A0@subsubsection AArch64 SVE registers feature

=C2=A0The @samp{org.gnu.gdb.aarch64.sve} feature is optional.=C2=A0 If pres= ent,
-it means the target supports the Scalable Vector Extension and must contai= n
+it means the target supports either the Scalable Vector Extension (SVE) or=
+the Scalable Matrix Extension (SME) and must contain
=C2=A0the following registers:

=C2=A0@itemize @minus
@@ -49780,6 +49781,14 @@ vector registers from the @samp{org.gnu.gdb.aarch6= 4.fpu} feature.
=C2=A0The first 128 bits of the @samp{z} registers overlap the 128 bits of = the
=C2=A0@samp{v} registers, so changing one will trigger a change to the othe= r.

+@samp{vg} represents the size of the @samp{z} registers, and is what
+the Arm architecture defines as the ``Effective SVE vector length''= ;. That
+means that if the target implements SME and is in streaming vector mode, +it is the streaming vector length. If the target implements only SME and +not SVE, and is not in streaming vector mode, then @samp{vg} is 2
+(indicating 128-bit vectors) and the @samp{z} registers match the @samp{v}=
+FPU registers.
+
=C2=A0For the types of the @samp{z}, @samp{p} and @samp{ffr} registers, ple= ase
=C2=A0check the aarch64-sve.c file.=C2=A0 No XML file is available for this= feature
=C2=A0because it is dynamically generated based on the current vector lengt= h.
@@ -49793,6 +49802,9 @@ aarch64-sve.c file, and should match what is descri= bed in aarch64-fpu.xml.
=C2=A0Extra registers are allowed in this feature, but they will not affect=
=C2=A0@value{GDBN}.

+The @samp{org.gnu.gdb.aarch64.sve} feature is required when the target als= o
+reports support for the @samp{org.gnu.gdb.aarch64.sme} feature.
+
=C2=A0@subsubsection AArch64 Pointer Authentication registers feature

=C2=A0The @samp{org.gnu.gdb.aarch64.pauth} optional feature was introduced = so
@@ -49948,6 +49960,10 @@ extensions of the architecture.
=C2=A0Extra registers are allowed in this feature, but they will not affect=
=C2=A0@value{GDBN}.

+Note that a target with only SME but not SVE support must still
+provide the @samp{org.gnu.gdb.aarch64.sve} feature, to expose the
+@samp{z} vector registers.
+
=C2=A0The @samp{org.gnu.gdb.aarch64.sme} feature is required when the targe= t also
=C2=A0reports support for the @samp{org.gnu.gdb.aarch64.sme2} feature.

--
2.43.0

Thanks. The documentation update looks OK given the current needs, bu= t I'm not too sure about keeping the SVE feature just for the Z registe= rs. I find that a bit confusing.

It might be cleaner to clearly separate SVE and SME features, add= ing Z registers to a SME feature if needed when SVE is disabled. Or somethi= ng similar to that.

I do= n't feel comfortable setting this is stone before we have a patch that = clarifies how this separation between SVE and SME is achieved.
--0000000000008b04d706498f1441--