From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27630 invoked by alias); 27 Aug 2014 09:07:48 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 27616 invoked by uid 89); 27 Aug 2014 09:07:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-oi0-f50.google.com Received: from mail-oi0-f50.google.com (HELO mail-oi0-f50.google.com) (209.85.218.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 27 Aug 2014 09:07:45 +0000 Received: by mail-oi0-f50.google.com with SMTP id a141so11697604oig.9 for ; Wed, 27 Aug 2014 02:07:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; 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charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-08/txt/msg00551.txt.bz2 On 13 August 2014 19:10, Will Newton wrote: > On 13 August 2014 14:12, Omair Javaid wrote: >> gdb: >> >> 2014-08-13 Omair Javaid >> >> * arm-tdep.c (arm_record_coproc_data_proc): Updated. >> (arm_record_asimd_vfp_coproc): Added record handler for asimd, vfp >> and coprocessor insn. >> (thumb2_record_coproc_insn): New function. >> (thumb2_record_decode_insn_handler): Updated. >> (decode_insn): Updated. >> >> --- >> gdb/arm-tdep.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++----- >> 1 file changed, 112 insertions(+), 10 deletions(-) >> >> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >> index b746eee..607b92e 100644 >> --- a/gdb/arm-tdep.c >> +++ b/gdb/arm-tdep.c >> @@ -11990,20 +11990,80 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) >> return -1; >> } >> >> +/* Handling opcode 110 insns. */ >> + >> +static int >> +arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) >> +{ >> + uint32_t op, op1, op1_sbit, op1_ebit, coproc; >> + >> + coproc = bits (arm_insn_r->arm_insn, 8, 11); >> + op1 = bits (arm_insn_r->arm_insn, 20, 25); >> + op1_sbit = bit (arm_insn_r->arm_insn, 24); >> + op1_ebit = bit (arm_insn_r->arm_insn, 20); >> + op = bit (arm_insn_r->arm_insn, 4); > > op abd op1_sbit appear to be unused. > >> + >> + if ((coproc & 0x0e) == 0x0a) >> + { >> + /* Handle extension register ld/st instructions. */ >> + if (!(op1 & 0x20)) >> + return arm_record_unsupported_insn (arm_insn_r); >> + >> + /* 64-bit transfers between arm core and extension registers. */ >> + if ((op1 & 0x3e) == 0x04) >> + return arm_record_unsupported_insn (arm_insn_r); >> + } >> + else >> + { >> + /* Handle coprocessor ld/st instructions. */ >> + if (!(op1 & 0x3a)) >> + { >> + /* Store. */ >> + if (!op1_ebit) >> + return arm_record_unsupported_insn (arm_insn_r); >> + else >> + /* Load. */ >> + return arm_record_unsupported_insn (arm_insn_r); >> + } >> + >> + /* Move to coprocessor from two arm core registers. */ >> + if (op1 == 0x4) >> + return arm_record_unsupported_insn (arm_insn_r); >> + >> + /* Move to two arm core registers from coprocessor. */ >> + if (op1 == 0x5) >> + { >> + uint32_t reg_t[2]; >> + >> + reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); >> + reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); >> + arm_insn_r->reg_rec_count = 2; >> + >> + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); >> + return 0; >> + } >> + } >> + return arm_record_unsupported_insn (arm_insn_r); >> +} >> + >> /* Handling opcode 111 insns. */ >> >> static int >> arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) >> { >> + uint32_t op, op1_sbit, op1_ebit, coproc; >> struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); >> struct regcache *reg_cache = arm_insn_r->regcache; >> - uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ >> ULONGEST u_regval = 0; >> >> arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); >> + coproc = bits (arm_insn_r->arm_insn, 8, 11); >> + op1_sbit = bit (arm_insn_r->arm_insn, 24); >> + op1_ebit = bit (arm_insn_r->arm_insn, 20); >> + op = bit (arm_insn_r->arm_insn, 4); >> >> /* Handle arm SWI/SVC system call instructions. */ >> - if (15 == arm_insn_r->opcode) >> + if (op1_sbit) >> { >> if (tdep->arm_syscall_record != NULL) >> { >> @@ -12016,21 +12076,52 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) >> else /* EABI. */ >> regcache_raw_read_unsigned (reg_cache, 7, &svc_number); >> >> - ret = tdep->arm_syscall_record (reg_cache, svc_number); >> + return tdep->arm_syscall_record (reg_cache, svc_number); >> } >> else >> { >> printf_unfiltered (_("no syscall record support\n")); >> - ret = -1; >> + return -1; >> } >> } >> + >> + if ((coproc & 0x0e) == 0x0a) >> + { >> + /* VFP data-processing instructions. */ >> + if (!op1_sbit && !op) >> + return arm_record_unsupported_insn (arm_insn_r); >> + >> + /* Advanced SIMD, VFP instructions. */ >> + if (!op1_sbit && op) >> + return arm_record_unsupported_insn (arm_insn_r); >> + } >> else >> { >> - arm_record_unsupported_insn (arm_insn_r); >> - ret = -1; >> + /* Coprocessor data operations. */ >> + if (!op1_sbit && !op) >> + return arm_record_unsupported_insn (arm_insn_r); >> + >> + /* Move to Coprocessor from ARM core register. */ >> + if (!op1_sbit && !op1_ebit && op) >> + return arm_record_unsupported_insn (arm_insn_r); >> + >> + /* Move to arm core register from coprocessor. */ >> + if (!op1_sbit && op1_ebit && op) >> + { >> + uint32_t record_buf[1]; >> + >> + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); >> + if (record_buf[0] == 15) >> + record_buf[0] = ARM_PS_REGNUM; >> + >> + arm_insn_r->reg_rec_count = 1; >> + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, >> + record_buf); >> + return 0; >> + } >> } >> >> - return ret; >> + return arm_record_unsupported_insn (arm_insn_r); >> } >> >> /* Handling opcode 000 insns. */ >> @@ -12946,6 +13037,17 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) >> return ARM_RECORD_SUCCESS; >> } >> >> +/* Record handler for thumb32 coprocessor instructions. */ >> + >> +static int >> +thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) >> +{ >> + if (bit (thumb2_insn_r->arm_insn, 25)) >> + return arm_record_coproc_data_proc (thumb2_insn_r); >> + else >> + return arm_record_asimd_vfp_coproc (thumb2_insn_r); >> +} >> + >> /* Decodes thumb2 instruction type and invokes its record handler. */ >> >> static unsigned int >> @@ -12977,7 +13079,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) >> else if (op2 & 0x40) >> { >> /* Co-processor instructions. */ >> - arm_record_unsupported_insn (thumb2_insn_r); >> + return thumb2_record_coproc_insn (thumb2_insn_r); >> } >> } >> else if (op1 == 0x02) >> @@ -13043,7 +13145,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) >> else if (op2 & 0x40) >> { >> /* Co-processor instructions. */ >> - return arm_record_unsupported_insn (thumb2_insn_r); >> + return thumb2_record_coproc_insn (thumb2_insn_r); >> } >> } >> >> @@ -13087,7 +13189,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, >> arm_record_ld_st_reg_offset, /* 011. */ >> arm_record_ld_st_multiple, /* 100. */ >> arm_record_b_bl, /* 101. */ >> - arm_record_unsupported_insn, /* 110. */ >> + arm_record_asimd_vfp_coproc, /* 110. */ >> arm_record_coproc_data_proc /* 111. */ >> }; >> >> -- >> 1.9.1 >> > > > > -- > Will Newton > Toolchain Working Group, Linaro Ping! Kindly provide your feedback and help me approve this patch series.