From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30679 invoked by alias); 27 Aug 2014 09:09:38 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 30615 invoked by uid 89); 27 Aug 2014 09:09:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-oa0-f53.google.com Received: from mail-oa0-f53.google.com (HELO mail-oa0-f53.google.com) (209.85.219.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 27 Aug 2014 09:09:36 +0000 Received: by mail-oa0-f53.google.com with SMTP id j17so12872456oag.40 for ; Wed, 27 Aug 2014 02:09:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; 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charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-08/txt/msg00554.txt.bz2 On 13 August 2014 19:10, Will Newton wrote: > On 13 August 2014 14:12, Omair Javaid wrote: >> gdb: >> >> 2014-08-13 Omair Javaid >> >> * arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for >> vector data transfer instructions. >> (arm_record_coproc_data_proc): Updated. >> >> --- >> gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- >> 1 file changed, 97 insertions(+), 1 deletion(-) > > Looks ok to me. > >> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >> index 315b5b0..7f651bc 100644 >> --- a/gdb/arm-tdep.c >> +++ b/gdb/arm-tdep.c >> @@ -11990,6 +11990,102 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) >> return -1; >> } >> >> +/* Record handler for vector data transfer instructions. */ >> + >> +static int >> +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) >> +{ >> + uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; >> + uint32_t record_buf[4]; >> + >> + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); >> + reg_t = bits (arm_insn_r->arm_insn, 12, 15); >> + reg_v = bits (arm_insn_r->arm_insn, 21, 23); >> + bits_a = bits (arm_insn_r->arm_insn, 21, 23); >> + bit_l = bit (arm_insn_r->arm_insn, 20); >> + bit_c = bit (arm_insn_r->arm_insn, 8); >> + >> + /* Handle VMOV instruction. */ >> + if (bit_l && bit_c) >> + { >> + record_buf[0] = reg_t; >> + arm_insn_r->reg_rec_count = 1; >> + } >> + else if (bit_l && !bit_c) >> + { >> + /* Handle VMOV instruction. */ >> + if (bits_a == 0x00) >> + { >> + if (bit (arm_insn_r->arm_insn, 20)) >> + record_buf[0] = reg_t; >> + else >> + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | >> + (reg_v << 1)); >> + >> + arm_insn_r->reg_rec_count = 1; >> + } >> + /* Handle VMRS instruction. */ >> + else if (bits_a == 0x07) >> + { >> + if (reg_t == 15) >> + reg_t = ARM_PS_REGNUM; >> + >> + record_buf[0] = reg_t; >> + arm_insn_r->reg_rec_count = 1; >> + } >> + } >> + else if (!bit_l && !bit_c) >> + { >> + /* Handle VMOV instruction. */ >> + if (bits_a == 0x00) >> + { >> + if (bit (arm_insn_r->arm_insn, 20)) >> + record_buf[0] = reg_t; >> + else >> + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | >> + (reg_v << 1)); >> + >> + arm_insn_r->reg_rec_count = 1; >> + } >> + /* Handle VMSR instruction. */ >> + else if (bits_a == 0x07) >> + { >> + record_buf[0] = ARM_FPSCR_REGNUM; >> + arm_insn_r->reg_rec_count = 1; >> + } >> + } >> + else if (!bit_l && bit_c) >> + { >> + /* Handle VMOV instruction. */ >> + if (!(bits_a & 0x04)) >> + { >> + record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) >> + + ARM_D0_REGNUM; >> + arm_insn_r->reg_rec_count = 1; >> + } >> + /* Handle VDUP instruction. */ >> + else >> + { >> + if (bit (arm_insn_r->arm_insn, 21)) >> + { >> + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); >> + record_buf[0] = reg_v + ARM_D0_REGNUM; >> + record_buf[1] = reg_v + ARM_D0_REGNUM + 1; >> + arm_insn_r->reg_rec_count = 2; >> + } >> + else >> + { >> + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); >> + record_buf[0] = reg_v + ARM_D0_REGNUM; >> + arm_insn_r->reg_rec_count = 1; >> + } >> + } >> + } >> + >> + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); >> + return 0; >> +} >> + >> /* Record handler for extension register load/store instructions. */ >> >> static int >> @@ -12467,7 +12563,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) >> >> /* Advanced SIMD, VFP instructions. */ >> if (!op1_sbit && op) >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_vdata_transfer_insn (arm_insn_r); >> } >> else >> { >> -- >> 1.9.1 >> > > > > -- > Will Newton > Toolchain Working Group, Linaro Ping! Kindly provide your feedback and help me approve this patch series.