From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5245 invoked by alias); 3 Jul 2012 19:15:08 -0000 Received: (qmail 5228 invoked by uid 22791); 3 Jul 2012 19:15:06 -0000 X-SWARE-Spam-Status: No, hits=-5.0 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-qc0-f169.google.com (HELO mail-qc0-f169.google.com) (209.85.216.169) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 03 Jul 2012 19:14:51 +0000 Received: by qcsd16 with SMTP id d16so4352103qcs.0 for ; Tue, 03 Jul 2012 12:14:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.202.67 with SMTP id fd3mr9885853qab.26.1341342890681; Tue, 03 Jul 2012 12:14:50 -0700 (PDT) Received: by 10.229.192.129 with HTTP; Tue, 3 Jul 2012 12:14:50 -0700 (PDT) In-Reply-To: References: <20120621181452.GA23413@intel.com> <201207031408.q63E8DbR009742@glazunov.sibelius.xs4all.nl> Date: Tue, 03 Jul 2012 19:15:00 -0000 Message-ID: Subject: Re: [PATCH 1/3] Add sp_regnum_from_eax and pc_regnum_from_eax From: "H.J. Lu" To: Mark Kettenis Cc: gdb-patches@sourceware.org Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-07/txt/msg00044.txt.bz2 On Tue, Jul 3, 2012 at 10:35 AM, H.J. Lu wrote: > On Tue, Jul 3, 2012 at 8:54 AM, H.J. Lu wrote: >> On Tue, Jul 3, 2012 at 7:08 AM, Mark Kettenis wrote: >>>> Date: Thu, 21 Jun 2012 11:14:52 -0700 >>>> From: "H.J. Lu" >>>> >>>> Hi, >>>> >>>> Here are the first of the last 3 patches for x32 support in GDB. This >>>> patch maps $pc to $eip and $sp to $esp for x32. OK to install? >>> >>> The pseudo register handling code is getting too complex :(. I feel >>> that hiding the set_gdbarch_pc_regnum() and set_gdbarch_sp_regnum() >>> calls in i386-tdep.c isn't the right approach. But I haven't found a >>> better one yet :(. >>> >> >> One possibility is to set pc/sp to register name instead of regnum. >> i386_gdbarch_init can map them to regnum after all pseudo registers >> are finalized. >> >> -- >> H.J. > > How about this patch? I can also change amd64 and i386 > to use "rsp/"rsp"/"esp"/"eip". > This patch sets SP?PC regnums from register names. -- H.J. --- * amd64-tdep.c (amd64_init_abi): Set sp_reg to "rsp" and pc_reg to "rip". Don't call set_gdbarch_sp_regnum nor set_gdbarch_pc_regnum here. (amd64_x32_init_abi): Set sp_reg to "esp" and pc_reg to "eip". * i386-tdep.c (i386_gdbarch_init): Set sp_reg to "esp" and pc_reg to "eip". Set SP regnum from sp_reg and PC regnum from pc_reg. * i386-tdep.h (gdbarch_tdep): Add sp_reg and pc_reg. diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 8ae1142..eeb21c3 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -2845,9 +2845,11 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); + /* Names of SP and PC registers. */ + tdep->sp_reg = "rsp"; + tdep->pc_reg = "rip"; + /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ - set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ @@ -2946,6 +2948,10 @@ amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdesc = tdesc_x32; tdep->tdesc = tdesc; + /* Names of SP and PC registers. */ + tdep->sp_reg = "esp"; + tdep->pc_reg = "eip"; + tdep->num_dword_regs = 17; set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index fd5969d..67805d3 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -7610,6 +7610,7 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) const struct target_desc *tdesc; int mm0_regnum; int ymm0_regnum; + int num_regs, regno, sp_pc_regs; /* If there is already a candidate, use it. */ arches = gdbarch_list_lookup_by_info (arches, &info); @@ -7670,9 +7671,11 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) alignment. */ set_gdbarch_long_double_bit (gdbarch, 96); + /* Names of SP and PC registers. */ + tdep->sp_reg = "esp"; + tdep->pc_reg = "eip"; + /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ - set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ @@ -7871,6 +7874,32 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else tdep->mm0_regnum = -1; + /* Set up SP and PC register numbers. */ + num_regs = (gdbarch_num_regs (gdbarch) + + gdbarch_num_pseudo_regs (gdbarch)); + sp_pc_regs = 0; + for (regno = 0; regno < num_regs; regno++) + { + const char *regname = tdesc_register_name (gdbarch, regno); + if (regname && regname[0] != '\0') + { + if ((sp_pc_regs & 0x1) == 0 + && strcmp (regname, tdep->sp_reg) == 0) + { + set_gdbarch_sp_regnum (gdbarch, regno); + sp_pc_regs |= 0x1; + } + else if ((sp_pc_regs & 0x2) == 0 + && strcmp (regname, tdep->pc_reg) == 0) + { + set_gdbarch_pc_regnum (gdbarch, regno); + sp_pc_regs |= 0x2; + } + } + if (sp_pc_regs == 0x3) + break; + } + /* Hook in the legacy prologue-based unwinders last (fallback). */ frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index 5f233f5..831f544 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -155,6 +155,12 @@ struct gdbarch_tdep /* Number of SSE registers. */ int num_xmm_regs; + /* Name for SP register. */ + const char *sp_reg; + + /* Name for PC register. */ + const char *pc_reg; + /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK register), excluding the x87 bit, which are supported by this GDB. */