From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6359 invoked by alias); 17 Dec 2012 17:37:16 -0000 Received: (qmail 6229 invoked by uid 22791); 17 Dec 2012 17:37:13 -0000 X-SWARE-Spam-Status: No, hits=-3.8 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-qc0-f182.google.com (HELO mail-qc0-f182.google.com) (209.85.216.182) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 17 Dec 2012 17:37:08 +0000 Received: by mail-qc0-f182.google.com with SMTP id k19so4103209qcs.13 for ; Mon, 17 Dec 2012 09:37:07 -0800 (PST) MIME-Version: 1.0 Received: by 10.224.201.73 with SMTP id ez9mr6614759qab.92.1355765827408; Mon, 17 Dec 2012 09:37:07 -0800 (PST) Received: by 10.49.12.210 with HTTP; Mon, 17 Dec 2012 09:37:07 -0800 (PST) In-Reply-To: <1355760101-26237-13-git-send-email-markus.t.metzger@intel.com> References: <1355760101-26237-1-git-send-email-markus.t.metzger@intel.com> <1355760101-26237-13-git-send-email-markus.t.metzger@intel.com> Date: Mon, 17 Dec 2012 17:37:00 -0000 Message-ID: Subject: Re: [patch v6 12/12] btrace, x86: disable on some processors From: "H.J. Lu" To: markus.t.metzger@intel.com Cc: jan.kratochvil@redhat.com, palves@redhat.com, tromey@redhat.com, kettenis@gnu.org, gdb-patches@sourceware.org, markus.t.metzger@gmail.com Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-12/txt/msg00578.txt.bz2 On Mon, Dec 17, 2012 at 8:01 AM, wrote: > From: Markus Metzger > > LBR, BTM, or BTS records may have incorrect branch "from" information afer an > EIST transition, T-states, C1E, or Adaptive Thermal Throttling (AAJ122). > > This results in sporadic test fails. Disable btrace on those processors. > > 2012-12-17 Markus Metzger > > * common/linux-btrace.c (linux_supports_btrace): Add cpuid check. > > > --- > gdb/common/linux-btrace.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 43 insertions(+), 0 deletions(-) > > diff --git a/gdb/common/linux-btrace.c b/gdb/common/linux-btrace.c > index 1231ccc..b5a41a5 100644 > --- a/gdb/common/linux-btrace.c > +++ b/gdb/common/linux-btrace.c > @@ -247,7 +247,50 @@ perf_event_read_bts (struct btrace_target_info* tinfo, const uint8_t *begin, > int > linux_supports_btrace (void) > { > +#if defined(__i386__) || defined(__x86_64__) > + { > + unsigned int cpuid, model, family; > + > + __asm__ __volatile__ ("movl $1, %%eax;" > + "cpuid;" > + : "=a" (cpuid) > + :: "%ebx", "%ecx", "%edx"); > + > + family = (cpuid >> 8) & 0xf; > + model = (cpuid >> 4) & 0xf; > > + switch (family) > + { > + case 6: > + model += (cpuid >> 12) & 0xf0; Do you need to verify that it is an Intel processor before checking extended family/model? > + switch (model) > + { > + case 26: /* Nehalem */ > + case 30: > + case 46: I believe model 31 is also Nehalem. BTW, most Intel documents use hex number, not decimal for model numbers. > + case 37: /* Westmere */ > + case 44: > + case 47: > + case 42: /* Sandy Bridge */ > + case 45: > + case 58: /* Ivy Bridge */ > + > + /* AAJ122: LBR, BTM, or BTS records may have incorrect branch > + "from" information afer an EIST transition, T-states, C1E, or > + Adaptive Thermal Throttling. */ > + return 0; > + } > + } > + } > + > return 1; > + > +#else /* defined(__i386__) || defined(__x86_64__) */ > + > + return 0; > + > +#endif /* defined(__i386__) || defined(__x86_64__) */ > } > > /* See linux-btrace.h. */ > -- > 1.7.6.5 > -- H.J.