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Date: Mon, 27 Feb 2012 18:49:00 -0000
Message-ID: <CAMe9rOp2x+pEJ5fcu5ipdQ=V-WwzQZp3zzZ83nCLiDQmihxMcA@mail.gmail.com>
Subject: Re: AVX and unavailable registers, fix system-gcore.exp
From: "H.J. Lu" <hjl.tools@gmail.com>
To: Pedro Alves <palves@redhat.com>
Cc: GDB Patches <gdb-patches@sourceware.org>, Mark Kettenis <mark.kettenis@xs4all.nl>
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On Thu, Jan 26, 2012 at 11:07 AM, Pedro Alves <palves@redhat.com> wrote:
> I now have access to a machine with AVX, and I'm seeing a few core related
> failures on native x86_64 Fedora 16. =A0GDBserver doesn't show the failur=
es because
> it treats this issue already like the patch below proposes.
>
> This was discussed a while ago, in the "RFC: partially available register=
s"
> thread:
>
> =A0http://old.nabble.com/RFC%3A-partially-available-registers-td32055573i=
20.html
>
> The failures I'm seeing look like, e.g.:
>
> FAIL: gdb.arch/system-gcore.exp: corefile restored all registers
>
> because before the core, the program showed:
>
> ...
> ymm0 =A0 =A0 =A0 =A0 =A0 *value not available*
> ...
>
> and when we load back the core we see:
>
> ...
> ymm0 =A0 =A0 =A0 =A0 =A0 {v8_float =3D {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=
, 0x0}, v4_double =3D {0x0, 0x0, 0x0, 0x0}, v32_int8 =3D {0x0 <repeats 32 t=
ime
> s>}, v16_int16 =3D {0x0 <repeats 16 times>}, v8_int32 =3D {0x0, 0x0, 0x0,=
 0x0, 0x0, 0x0, 0x0, 0x0}, v4_int64 =3D {0x0, 0x0, 0x0, 0x0}, v2_int
> 128 =3D {0x00000000000000000000000000000000, 0x00000000000000000000000000=
000000}}
> ...
>
>
> I think we should make live debugging present the still-not-touched x87
> states as zero, as described in the comment in the patch:
>
> + =A0/* With the delayed xsave mechanism, in between the program
> + =A0 =A0 starting, and the program accessing the vector registers for the
> + =A0 =A0 first time, the register's values are invalid. =A0The kernel
> + =A0 =A0 initializes register states to zero when they are set the first
> + =A0 =A0 time in a program. =A0This means that from the user-space progr=
ams'
> + =A0 =A0 perspective, it's the same as if the registers have always been
> + =A0 =A0 zero from the start of the program. =A0Therefore, the debugger
> + =A0 =A0 should provide the same illusion to the user.
>
> This is already handled this way with gdbserver, hence we don't see
> these failures there (the gcore tests now work against gdbserver).
> The kernel is also putting the registers touched as zero
> in the core, otherwise we'd see *unavailable* when we loaded the
> core file back.
>
>
> I have a doubt in the xsave-in-corefile support bits. =A0There's code in =
place to
> handle a NULL regs (as in no xsave contents to work with), so I'm handlin=
g it
> as presently:
>
> +
> + =A0 =A0 Note however, the case when REGS is NULL is a different case.
> + =A0 =A0 That case means we do not have access to the x87 states, so we
> + =A0 =A0 should mark the registers as unavailable (by supplying NULL). =
=A0*/
> +
>
> but I can't figure out how would we ever get a NULL REGS there. =A0Is the=
re a
> convoluted path I missed? =A0amd64-linux-tdep.c unconditionally installs
> amd64_linux_regset_sections as gdbarch_core_regset_sections
> callback, and this includes the .reg-xstate section.
> However, corelow.c:get_core_register_section bails early if
> a section is not found in the core, never reaching regset->supply_regset
> with a NULL `contents'.
>
> Mark, maybe you have a clue?
>
> --
> Pedro Alves
>
> 2012-01-26 =A0Pedro Alves =A0<palves@redhat.com>
>
> =A0 =A0 =A0 =A0* i387-tdep.c (i387_supply_xsave): If we have an xsave buf=
fer, and
> =A0 =A0 =A0 =A0the register state is clear, supply explicit zero, instead=
 of
> =A0 =A0 =A0 =A0marking the register unavailable.

This fixes 7.3/7.4 regression:

http://www.sourceware.org/bugzilla/show_bug.cgi?id=3D13766

> ---
>
> =A0gdb/i387-tdep.c | =A0 87 ++++++++++++++++++++++++++++++++++-----------=
----------
> =A01 files changed, 54 insertions(+), 33 deletions(-)
>
> diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c
> index 450b8f2..b3adb74 100644
> --- a/gdb/i387-tdep.c
> +++ b/gdb/i387-tdep.c
> @@ -725,6 +725,7 @@ i387_supply_xsave (struct regcache *regcache, int reg=
num,
> =A0 const gdb_byte *regs =3D xsave;
> =A0 int i;
> =A0 unsigned int clear_bv;
> + =A0const gdb_byte zero[MAX_REGISTER_SIZE] =3D { 0 };

Shouldn't it be static since it is never modified?

> =A0 const gdb_byte *p;
> =A0 enum
> =A0 =A0 {
> @@ -764,6 +765,19 @@ i387_supply_xsave (struct regcache *regcache, int re=
gnum,
> =A0 else
> =A0 =A0 clear_bv =3D I386_XSTATE_AVX_MASK;
>
> + =A0/* With the delayed xsave mechanism, in between the program
> + =A0 =A0 starting, and the program accessing the vector registers for the
> + =A0 =A0 first time, the register's values are invalid. =A0The kernel
> + =A0 =A0 initializes register states to zero when they are set the first
> + =A0 =A0 time in a program. =A0This means that from the user-space progr=
ams'
> + =A0 =A0 perspective, it's the same as if the registers have always been
> + =A0 =A0 zero from the start of the program. =A0Therefore, the debugger
> + =A0 =A0 should provide the same illusion to the user.
> +
> + =A0 =A0 Note however, the case when REGS is NULL is a different case.
> + =A0 =A0 That case means we do not have access to the x87 states, so we
> + =A0 =A0 should mark the registers as unavailable (by supplying NULL). =
=A0*/
> +
> =A0 switch (regclass)
> =A0 =A0 {
> =A0 =A0 case none:
> @@ -771,26 +785,26 @@ i387_supply_xsave (struct regcache *regcache, int r=
egnum,
>
> =A0 =A0 case avxh:
> =A0 =A0 =A0 if ((clear_bv & I386_XSTATE_AVX))
> - =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum, regs =3D=3D NULL ? N=
ULL : zero);
> =A0 =A0 =A0 else
> - =A0 =A0 =A0 p =3D XSAVE_AVXH_ADDR (tdep, regs, regnum);
> - =A0 =A0 =A0regcache_raw_supply (regcache, regnum, p);
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XSAVE_AVXH_ADDR =
(tdep, regs, regnum));
> =A0 =A0 =A0 return;
>
> =A0 =A0 case sse:
> =A0 =A0 =A0 if ((clear_bv & I386_XSTATE_SSE))
> - =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum, regs =3D=3D NULL ? N=
ULL : zero);
> =A0 =A0 =A0 else
> - =A0 =A0 =A0 p =3D FXSAVE_ADDR (tdep, regs, regnum);
> - =A0 =A0 =A0regcache_raw_supply (regcache, regnum, p);
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0FXSAVE_ADDR (tde=
p, regs, regnum));
> =A0 =A0 =A0 return;
>
> =A0 =A0 case x87:
> =A0 =A0 =A0 if ((clear_bv & I386_XSTATE_X87))
> - =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum, regs =3D=3D NULL ? N=
ULL : zero);
> =A0 =A0 =A0 else
> - =A0 =A0 =A0 p =3D FXSAVE_ADDR (tdep, regs, regnum);
> - =A0 =A0 =A0regcache_raw_supply (regcache, regnum, p);
> + =A0 =A0 =A0 regcache_raw_supply (regcache, regnum,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0FXSAVE_ADDR (tde=
p, regs, regnum));
> =A0 =A0 =A0 return;
>
> =A0 =A0 case all:
> @@ -798,16 +812,19 @@ i387_supply_xsave (struct regcache *regcache, int r=
egnum,
> =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_AVX))
> =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0if ((clear_bv & I386_XSTATE_AVX))
> - =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_YMM0H_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_YMMENDH_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, regs =3D=
=3D NULL ? NULL : zero);
> + =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0else
> - =A0 =A0 =A0 =A0 =A0 p =3D regs;
> -
> - =A0 =A0 =A0 =A0 for (i =3D I387_YMM0H_REGNUM (tdep);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_YMMENDH_REGNUM (tdep); i++)
> =A0 =A0 =A0 =A0 =A0 =A0{
> - =A0 =A0 =A0 =A0 =A0 =A0 if (p !=3D NULL)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D XSAVE_AVXH_ADDR (tdep, regs, i);
> - =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, p);
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_YMM0H_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_YMMENDH_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
XSAVE_AVXH_ADDR (tdep, regs, i));
> =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0}
>
> @@ -815,16 +832,18 @@ i387_supply_xsave (struct regcache *regcache, int r=
egnum,
> =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_SSE))
> =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0if ((clear_bv & I386_XSTATE_SSE))
> - =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_XMM0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_MXCSR_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, regs =3D=
=3D NULL ? NULL : zero);
> + =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0else
> - =A0 =A0 =A0 =A0 =A0 p =3D regs;
> -
> - =A0 =A0 =A0 =A0 for (i =3D I387_XMM0_REGNUM (tdep);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_MXCSR_REGNUM (tdep); i++)
> =A0 =A0 =A0 =A0 =A0 =A0{
> - =A0 =A0 =A0 =A0 =A0 =A0 if (p !=3D NULL)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D FXSAVE_ADDR (tdep, regs, i);
> - =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, p);
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_XMM0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_MXCSR_REGNUM (tdep); i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
FXSAVE_ADDR (tdep, regs, i));
> =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0}
>
> @@ -832,16 +851,18 @@ i387_supply_xsave (struct regcache *regcache, int r=
egnum,
> =A0 =A0 =A0 if ((tdep->xcr0 & I386_XSTATE_X87))
> =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0if ((clear_bv & I386_XSTATE_X87))
> - =A0 =A0 =A0 =A0 =A0 p =3D NULL;
> + =A0 =A0 =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_ST0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_FCTRL_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, regs !=3D=
 NULL ? zero : NULL);
> + =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0else
> - =A0 =A0 =A0 =A0 =A0 p =3D regs;
> -
> - =A0 =A0 =A0 =A0 for (i =3D I387_ST0_REGNUM (tdep);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_FCTRL_REGNUM (tdep); i++)
> =A0 =A0 =A0 =A0 =A0 =A0{
> - =A0 =A0 =A0 =A0 =A0 =A0 if (p !=3D NULL)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 p =3D FXSAVE_ADDR (tdep, regs, i);
> - =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, p);
> + =A0 =A0 =A0 =A0 =A0 =A0 for (i =3D I387_ST0_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i < I387_FCTRL_REGNUM (tdep);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i++)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 regcache_raw_supply (regcache, i, FXSAVE_AD=
DR (tdep, regs, i));
> =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 break;



--=20
H.J.