From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x344.google.com (mail-ot1-x344.google.com [IPv6:2607:f8b0:4864:20::344]) by sourceware.org (Postfix) with ESMTPS id AB6B83AA7CAE for ; Fri, 13 Mar 2020 01:29:55 +0000 (GMT) Received: by mail-ot1-x344.google.com with SMTP id 66so8440300otd.9 for ; Thu, 12 Mar 2020 18:29:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qbae8EISGYwF42UYTDtvp6pCohgMa4YEbv08pXuPdOE=; b=mh6E4VLRPALmAmjVWksLmnCBokWRTG6O0acqFlIE0WxOVP3jAleSo9XHV64/jcBZTV RdOq/ljLPNR8sGRdXrOu/6kc66wO8VUfklCsVC6reuBS7rWNsloSxZbrg1RH1Sxu0U99 WXXXGxOEbz8RgypVkVvWiy3G4MWun1Lg6WD40jSp01kyICp0rKkIttZJbrf1VI312bqD VLkx9lOSlTaIoe0qxIFtf8T35nZmzH5+05Z21eFWic6Kxm0b5nCVkaB8XdLTjzkcoBel 9u++yHQ+zT5+/r03ownbCah/qdVPz46h3Mvv1kQacTVz8H85SMZhz44MjsgkD4Ip4RPq OuvA== X-Gm-Message-State: ANhLgQ0TV4Trz7/BIq4zOvRUEHEK6w031HZ6d6MIQHumg/ZEyKA92D7t dBJpOIFYx/x4L3gFk/NO7gtOwGe6eKCWpJ4ftjc= X-Google-Smtp-Source: ADFU+vvPFsQRz+pPoF2+WzIGazE071bkAUYYyV4vEEZRTYABjh1cV9ni+BrZbf3zO/lRVA/7wznBiZb9ItideFlMy+g= X-Received: by 2002:a9d:21c5:: with SMTP id s63mr8575215otb.142.1584062995013; Thu, 12 Mar 2020 18:29:55 -0700 (PDT) MIME-Version: 1.0 References: <20200313005852.14788-1-vcollod@nvidia.com> In-Reply-To: <20200313005852.14788-1-vcollod@nvidia.com> From: "H.J. Lu" Date: Thu, 12 Mar 2020 18:29:18 -0700 Message-ID: Subject: Re: [PATCH] Add support for intel IBT To: Victor Collod Cc: GDB Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Mar 2020 01:29:56 -0000 On Thu, Mar 12, 2020 at 5:59 PM Victor Collod via Gdb-patches wrote: > > Intel IBT adds a new instruction that is used to mark valid indirect > jump targets. Some recent compilers add such instructions at the > beginning of all functions. > > Without this patch, gdb does not properly skip the prologue of these > functions, which makes it fail to print function arguments right after > hitting a function breakpoint. > > 2020-03-12 Victor Collod > > * i386-tdep.c (i386_skip_endbr): add a helper function to skip endbr > instructions. > (i386_analyze_prologue): call i386_skip_endbr. > * amd64-tdep.c (i386_analyze_prologue): skip endbr instructions. > --- > gdb/amd64-tdep.c | 74 ++++++++++++++++++++++++++++-------------------- > gdb/i386-tdep.c | 19 +++++++++++++ > 2 files changed, 62 insertions(+), 31 deletions(-) > > diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c > index 5c56a970d8..bce6dcda47 100644 > --- a/gdb/amd64-tdep.c > +++ b/gdb/amd64-tdep.c > @@ -2375,12 +2375,13 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, > /* There are two variations of movq %rsp, %rbp. */ > static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; > static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; > + static const gdb_byte endbr64[4] = { 0xf3, 0x0f, 0x1e, 0xfa }; > + > /* Ditto for movl %esp, %ebp. */ > static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; > static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; > > - gdb_byte buf[3]; > - gdb_byte op; > + gdb_byte buf[4]; > > if (current_pc <= pc) > return current_pc; > @@ -2390,43 +2391,54 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, > else > pc = amd64_analyze_stack_align (pc, current_pc, cache); > > - op = read_code_unsigned_integer (pc, 1, byte_order); > - > - if (op == 0x55) /* pushq %rbp */ > + /* Check for an IBT ENDBRANCH instruction */ > + read_code (pc, buf, sizeof(endbr64)); > + if (memcmp (buf, endbr64, sizeof(endbr64)) == 0) > { > - /* Take into account that we've executed the `pushq %rbp' that > - starts this instruction sequence. */ > - cache->saved_regs[AMD64_RBP_REGNUM] = 0; > - cache->sp_offset += 8; > - > + pc += sizeof(endbr64); > /* If that's all, return now. */ > - if (current_pc <= pc + 1) > - return current_pc; > + if (current_pc <= pc) > + return current_pc; > + } > + > + /* stop right now if there's no `pushq %rbp' */ > + if (read_code_unsigned_integer (pc, 1, byte_order) != 0x55) > + return pc; > + > + /* Take into account that we've executed the `pushq %rbp' that > + starts this instruction sequence. */ > + cache->saved_regs[AMD64_RBP_REGNUM] = 0; > + cache->sp_offset += 8; > + > + pc += 1; > + > + /* If that's all, return now. */ > + if (current_pc <= pc) > + return current_pc; > > - read_code (pc + 1, buf, 3); > + read_code (pc, buf, 3); > > - /* Check for `movq %rsp, %rbp'. */ > - if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 > - || memcmp (buf, mov_rsp_rbp_2, 3) == 0) > + /* Check for `movq %rsp, %rbp'. */ > + if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 > + || memcmp (buf, mov_rsp_rbp_2, 3) == 0) > + { > + pc += 3; > + /* OK, we actually have a frame. */ > + cache->frameless_p = 0; > + return pc; > + } > + > + /* For X32, also check for `movq %esp, %ebp'. */ It should be "movl %esp, %ebp", not movq. > + if (gdbarch_ptr_bit (gdbarch) == 32) > + { > + if (memcmp (buf, mov_esp_ebp_1, 2) == 0 > + || memcmp (buf, mov_esp_ebp_2, 2) == 0) > { > + pc += 2; > /* OK, we actually have a frame. */ > cache->frameless_p = 0; > - return pc + 4; > + return pc; > } > - > - /* For X32, also check for `movq %esp, %ebp'. */ > - if (gdbarch_ptr_bit (gdbarch) == 32) > - { > - if (memcmp (buf, mov_esp_ebp_1, 2) == 0 > - || memcmp (buf, mov_esp_ebp_2, 2) == 0) > - { > - /* OK, we actually have a frame. */ > - cache->frameless_p = 0; > - return pc + 3; > - } > - } > - > - return pc + 1; > } > > return pc; -- H.J.