From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9707 invoked by alias); 3 Jul 2012 17:35:48 -0000 Received: (qmail 9361 invoked by uid 22791); 3 Jul 2012 17:35:45 -0000 X-SWARE-Spam-Status: No, hits=-5.0 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-qa0-f41.google.com (HELO mail-qa0-f41.google.com) (209.85.216.41) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 03 Jul 2012 17:35:30 +0000 Received: by qabg27 with SMTP id g27so3154996qab.0 for ; Tue, 03 Jul 2012 10:35:29 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.78.195 with SMTP id m3mr14705914qak.1.1341336929121; Tue, 03 Jul 2012 10:35:29 -0700 (PDT) Received: by 10.229.192.129 with HTTP; Tue, 3 Jul 2012 10:35:29 -0700 (PDT) In-Reply-To: References: <20120621181452.GA23413@intel.com> <201207031408.q63E8DbR009742@glazunov.sibelius.xs4all.nl> Date: Tue, 03 Jul 2012 17:35:00 -0000 Message-ID: Subject: Re: [PATCH 1/3] Add sp_regnum_from_eax and pc_regnum_from_eax From: "H.J. Lu" To: Mark Kettenis Cc: gdb-patches@sourceware.org Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-07/txt/msg00042.txt.bz2 On Tue, Jul 3, 2012 at 8:54 AM, H.J. Lu wrote: > On Tue, Jul 3, 2012 at 7:08 AM, Mark Kettenis wrote: >>> Date: Thu, 21 Jun 2012 11:14:52 -0700 >>> From: "H.J. Lu" >>> >>> Hi, >>> >>> Here are the first of the last 3 patches for x32 support in GDB. This >>> patch maps $pc to $eip and $sp to $esp for x32. OK to install? >> >> The pseudo register handling code is getting too complex :(. I feel >> that hiding the set_gdbarch_pc_regnum() and set_gdbarch_sp_regnum() >> calls in i386-tdep.c isn't the right approach. But I haven't found a >> better one yet :(. >> > > One possibility is to set pc/sp to register name instead of regnum. > i386_gdbarch_init can map them to regnum after all pseudo registers > are finalized. > > -- > H.J. How about this patch? I can also change amd64 and i386 to use "rsp/"rsp"/"esp"/"eip". Thanks. -- H.J. --- * amd64-tdep.c (amd64_x32_init_abi): Set sp_pseudo_reg to "esp" and pc_pseudo_reg to "eip". * i386-tdep.c (i386_gdbarch_init): Initialize sp_pseudo_reg and pc_pseudo_reg to NULL. Update SP regnum from sp_pseudo_reg and PC regnum from pc_pseudo_reg if needed. * i386-tdep.h (gdbarch_tdep): Add sp_pseudo_reg and pc_pseudo_reg. diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 8ae1142..d59b8c1 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -2946,6 +2946,9 @@ amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdesc = tdesc_x32; tdep->tdesc = tdesc; + tdep->sp_pseudo_reg = "esp"; + tdep->pc_pseudo_reg = "eip"; + tdep->num_dword_regs = 17; set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index fd5969d..a9fee8f 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -7610,6 +7610,7 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) const struct target_desc *tdesc; int mm0_regnum; int ymm0_regnum; + int num_sp_pc_regs; /* If there is already a candidate, use it. */ arches = gdbarch_list_lookup_by_info (arches, &info); @@ -7805,6 +7806,9 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->num_mmx_regs = 8; tdep->num_ymm_regs = 0; + tdep->sp_pseudo_reg = NULL; + tdep->pc_pseudo_reg = NULL; + tdesc_data = tdesc_data_alloc (); set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); @@ -7871,6 +7875,43 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else tdep->mm0_regnum = -1; + /* Check pseudo SP/PC register support. */ + num_sp_pc_regs = 0; + if (tdep->sp_pseudo_reg != NULL) + num_sp_pc_regs++; + if (tdep->pc_pseudo_reg != NULL) + num_sp_pc_regs++; + + if (num_sp_pc_regs) + { + int num_regs = gdbarch_num_regs (gdbarch); + int num_pseudo_regs = gdbarch_num_pseudo_regs (gdbarch); + int regno, sp_pc_regs = 0; + const char *regname; + + for (regno = num_regs; + regno < num_regs + num_pseudo_regs; + regno++) + { + regname = tdesc_register_name (gdbarch, regno); + if (regname && regname[0] != '\0') + { + if (strcmp (regname, tdep->sp_pseudo_reg) == 0) + { + set_gdbarch_sp_regnum (gdbarch, regno); + sp_pc_regs++; + } + else if (strcmp (regname, tdep->pc_pseudo_reg) == 0) + { + set_gdbarch_pc_regnum (gdbarch, regno); + sp_pc_regs++; + } + } + if (sp_pc_regs == num_sp_pc_regs) + break; + } + } + /* Hook in the legacy prologue-based unwinders last (fallback). */ frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index 5f233f5..6e53ff1 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -155,6 +155,14 @@ struct gdbarch_tdep /* Number of SSE registers. */ int num_xmm_regs; + /* Pseudo register name for SP. Set this to NULL to disable pseudo SP + register support. */ + const char *sp_pseudo_reg; + + /* Pseudo register name for PC. Set this to NULL to disable pseudo PC + register support. */ + const char *pc_pseudo_reg; + /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK register), excluding the x87 bit, which are supported by this GDB. */