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AJvYcCWEROvaej12/xGj3kdQwKEQhotUUr9WCTKZF4mGfmAoZJ0D1jsESUgtdnsJm3aAVjzF71W8V8DFgOTl+A==@sourceware.org X-Gm-Message-State: AOJu0Yy/hcBDRG+/qkLnAJYvmcT8bdrRh2hRqkRlOWiUj4AVi/tgW3jC 9tvqPkumZ0+55o7pQxmWXIV7EPnTJ5dv0TGrr2HSaPtKVDzZkOgyjKi4irSMOu8V5ifvG9nzDkK WcCNG8TVSnPhxonu0mOQ++eJcfV0A/g6awTvwaFa0Mu7V2XDill4mZS8= X-Gm-Gg: ASbGncvq+IKy6w42evsxzpO5/DA7Ya7229GCAK8E4KrOLx8aqWKW0Dp4Bv4qQ4vGnO2 mJ8klbkvL/tWcvwCVu78Rqv10AkSZWrSxaisVPzX3Mw7+AncXAFUh5UEovwBN+lYvA6geMIjFFs oCleU/SYnX0uTX49u7Nou23pNOmuTy379WTm33X5w0FLC14pQwJjKpgAM1BFpxBx3ix6/+jg539 loIKvNrzF1nbl0bhgYQdzfxritf7A== X-Google-Smtp-Source: AGHT+IFvzKh/4Qeb3BgMlZnzrQyBlEcIWzo/H4106we8ihYYMxOcbVom/6vW3UJHHAp/P9+DnQAQdFiYNGregpsOTls= X-Received: by 2002:a05:6402:3881:b0:61c:5b3f:4d69 with SMTP id 4fb4d7f45d1cf-61d2688c061mr18550951a12.11.1757066289662; Fri, 05 Sep 2025 02:58:09 -0700 (PDT) MIME-Version: 1.0 References: <3bdebc70-e678-44e7-98ec-18c6b23dccca@simark.ca> <93642dcc-4922-4a15-84ae-2404e9d54a17@simark.ca> <9e20ab3e-b7d2-42d8-9444-1985e75f60bd@suse.de> In-Reply-To: <9e20ab3e-b7d2-42d8-9444-1985e75f60bd@suse.de> From: Gopi Kumar Bulusu Date: Fri, 5 Sep 2025 14:57:36 +0530 X-Gm-Features: Ac12FXxW27ikjM4krO30_k8jZmrKfKtra0LWtAbh1AF7KwtVs8dsG3JZ5lIaQZg Message-ID: Subject: Re: [PATCH v2 ] MicroBlaze: Add microblaze_get_next_pcs To: Tom de Vries Cc: Simon Marchi , gdb-patches@sourceware.org, Michael Eager Content-Type: multipart/alternative; boundary="0000000000000adec5063e0ae0e0" X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org --0000000000000adec5063e0ae0e0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Sep 5, 2025 at 2:59=E2=80=AFPM Tom de Vries wrot= e: > On 9/3/25 19:57, Simon Marchi wrote: > > On 9/2/25 8:27 AM, Gopi Kumar Bulusu wrote: > >> From 7f2bacc6fffa6830991da36c2044431237bacba1 Mon Sep 17 00:00:00 200= 1 > >> From: Gopi Kumar Bulusu > >> Date: Tue, 12 Aug 2025 09:42:48 +0530 > >> Subject: [PATCH v2] MicroBlaze: Add microblaze_get_next_pcs > >> > >> This patch enables software single stepping for gdbserver target > >> > >> * gdb/microblaze-tdep.c: Add microblaze_get_next_pcs > >> > >> Signed-off-by: David Holsgrove > >> Signed-off-by: Nathan Rossi > >> Signed-off-by: Mahesh Bodapati > >> Signed-off-by: Gopi Kumar Bulusu > >> --- > >> gdb/microblaze-tdep.c | 91 +++++++++++++++++++++++++++++++++++++++++= ++ > >> 1 file changed, 91 insertions(+) > >> > >> diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c > >> index 7b58220871c..cacec8ba186 100644 > >> --- a/gdb/microblaze-tdep.c > >> +++ b/gdb/microblaze-tdep.c > >> @@ -590,6 +590,95 @@ microblaze_stabs_argument_has_addr (struct gdbarc= h > *gdbarch, struct type *type) > >> return (type->length () =3D=3D 16); > >> } > >> > >> +/* Return next pc values : next in sequence and/or branch/return > target. */ > >> + > >> +static std::vector > >> +microblaze_get_next_pcs (regcache *regcache) > >> +{ > >> + CORE_ADDR pc =3D regcache_read_pc (regcache); > >> + long insn =3D microblaze_fetch_instruction (pc); > >> + > >> + enum microblaze_instr_type insn_type; > >> + short delay_slots; > >> + bool isunsignednum; > >> + > >> + /* If the current instruction is an imm, look at the inst after. *= / > >> + > >> + get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots= ); > >> + > >> + int imm; > >> + bool immfound =3D false; > >> + > >> + if (insn_type =3D=3D immediate_inst) > >> + { > >> + int rd, ra, rb; > >> + immfound =3D true; > >> + microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); > >> + pc +=3D INST_WORD_SIZE; > >> + insn =3D microblaze_fetch_instruction (pc); > >> + get_insn_microblaze (insn, &isunsignednum, &insn_type, > &delay_slots); > >> + } > >> + > >> + std::optional next_pc, branch_or_return_pc; > >> + > >> + /* Compute next instruction address - skip delay slots if any. */ > >> + > >> + if (insn_type !=3D return_inst) > >> + next_pc =3D pc + INST_WORD_SIZE + (delay_slots * INST_WORD_SIZE); > >> + > >> + microblaze_debug ("single-step insn_type=3D0x%x pc=3D0x%lx insn=3D0= x%lx\n", > >> + insn_type, pc, insn); > > > > You shouldn't need the trailing \n. Apply elsewhere too. > > > >> + > >> + /* Compute target instruction address for branch or return > instruction. */ > >> + if (insn_type =3D=3D branch_inst || insn_type =3D=3D return_inst) > >> + { > >> + int limm; > >> + int lrd, lra, lrb; > >> + long ra, rb; > >> + bool targetvalid; > >> + bool unconditionalbranch; > > > > Declare when first use, where possible (ra and rb). > > > > ra and rb should probably be of the type ULONGEST. > > > >> + > >> + microblaze_decode_insn (insn, &lrd, &lra, &lrb, &limm); > >> + ra =3D regcache_raw_get_unsigned (regcache, lra); > >> + rb =3D regcache_raw_get_unsigned (regcache, lrb); > >> + > >> + branch_or_return_pc =3D microblaze_get_target_address (insn, > immfound, > >> + imm, pc, ra, rb, &targetvalid, &unconditionalbranch= ); > > > > Format like this: > > > > branch_or_return_pc > > =3D microblaze_get_target_address (insn, immfound, > > imm, pc, ra, rb, &targetvalid, > > &unconditionalbranch); > > > >> + > >> + microblaze_debug ( > >> + "single-step uncondbr=3D%d targetvalid=3D%d > target=3D0x%lx\n", > >> + unconditionalbranch, targetvalid, > >> + branch_or_return_pc.value () ); > > > > Format like this: > > > > microblaze_debug ("single-step uncondbr=3D%d targetvalid=3D%d > target=3D0x%lx", > > unconditionalbranch, targetvalid, > > branch_or_return_pc.value ()); > > > >> + > >> + /* Can't reach next address. */ > >> + if (unconditionalbranch) > >> + next_pc.reset (); > >> + > >> + /* Can't reach a distinct (not here) target address. */ > >> + if (! targetvalid || branch_or_return_pc =3D=3D pc || > >> + (next_pc && (branch_or_return_pc =3D=3D next_pc))) > >> + branch_or_return_pc.reset (); > > > > Format like this: > > > > /* Can't reach a distinct (not here) target address. */ > > if (!targetvalid > > || branch_or_return_pc =3D=3D pc > > || (next_pc.has_value () && branch_or_return_pc =3D=3D next_pc)= ) > > branch_or_return_pc.reset (); > > > > > >> + } /* if (branch or return instruction). */ > >> + > >> + /* Create next_pcs vector to return. */ > >> + > >> + std::vector next_pcs; > >> + > >> + if (next_pc) > > > > .has_value () > > > >> + { > >> + next_pcs.push_back (next_pc.value () ); > > > > We typically use `*next_pc` to access the value (apply elsewhere too). > > > > Remove the space before closing parenthesis (apply elsewhere too). > > > >> + microblaze_debug ("push_back next_pc(0x%lx)\n", next_pc.value (= ) > ); > >> + } > >> + > >> + if (branch_or_return_pc) > >> + { > >> + next_pcs.push_back ( branch_or_return_pc.value () ); > >> + microblaze_debug ("push_back branch_or_return_pc(0x%lx)\n", > >> + branch_or_return_pc.value ()); > > > > Align the last line properly. > > > > The patch LGTM with those fixed. Let me know if you need help pushing > > the patch. > > > > This caused a buildbreaker on arm-linux with --enable-targets=3Dall and > --enable-64-bit-bfd. > > reverted commit c6df5d79aac5c4a77c06314fd26c837470360f70 dhanyavaadaaha gopi I've filed a PR ( https://sourceware.org/bugzilla/show_bug.cgi?id=3D33381 )= . > Thanks, > - Tom > > > Approved-By: Simon Marchi > > > > Simon > > --0000000000000adec5063e0ae0e0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Fri, Sep 5, = 2025 at 2:59=E2=80=AFPM Tom de Vries <tdevries@suse.de> wrote:
On 9/3/25 19:57, Simon Marchi wrote:
> On 9/2/25 8:27 AM, Gopi Kumar Bulusu wrote:
>>=C2=A0 From 7f2bacc6fffa6830991da36c2044431237bacba1 Mon Sep 17 00:= 00:00 2001
>> From: Gopi Kumar Bulusu <gopi@sankhya.com>
>> Date: Tue, 12 Aug 2025 09:42:48 +0530
>> Subject: [PATCH v2] MicroBlaze: Add microblaze_get_next_pcs
>>
>> This patch enables software single stepping for gdbserver target >>
>> * gdb/microblaze-tdep.c: Add microblaze_get_next_pcs
>>
>> Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com> >> Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
>> Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
>> Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
>> ---
>>=C2=A0 =C2=A0gdb/microblaze-tdep.c | 91 +++++++++++++++++++++++++++= ++++++++++++++++
>>=C2=A0 =C2=A01 file changed, 91 insertions(+)
>>
>> diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
>> index 7b58220871c..cacec8ba186 100644
>> --- a/gdb/microblaze-tdep.c
>> +++ b/gdb/microblaze-tdep.c
>> @@ -590,6 +590,95 @@ microblaze_stabs_argument_has_addr (struct gd= barch *gdbarch, struct type *type)
>>=C2=A0 =C2=A0 =C2=A0return (type->length () =3D=3D 16);
>>=C2=A0 =C2=A0}
>>=C2=A0 =C2=A0
>> +/* Return next pc values : next in sequence and/or branch/return = target.=C2=A0 */
>> +
>> +static std::vector<CORE_ADDR>
>> +microblaze_get_next_pcs (regcache *regcache)
>> +{
>> +=C2=A0 CORE_ADDR pc =3D regcache_read_pc (regcache);
>> +=C2=A0 long insn =3D microblaze_fetch_instruction (pc);
>> +
>> +=C2=A0 enum microblaze_instr_type insn_type;
>> +=C2=A0 short delay_slots;
>> +=C2=A0 bool isunsignednum;
>> +
>> +=C2=A0 /* If the current instruction is an imm, look at the inst = after.=C2=A0 */
>> +
>> +=C2=A0 get_insn_microblaze (insn, &isunsignednum, &insn_t= ype, &delay_slots);
>> +
>> +=C2=A0 int imm;
>> +=C2=A0 bool immfound =3D false;
>> +
>> +=C2=A0 if (insn_type =3D=3D immediate_inst)
>> +=C2=A0 =C2=A0 {
>> +=C2=A0 =C2=A0 =C2=A0 int rd, ra, rb;
>> +=C2=A0 =C2=A0 =C2=A0 immfound =3D true;
>> +=C2=A0 =C2=A0 =C2=A0 microblaze_decode_insn (insn, &rd, &= ra, &rb, &imm);
>> +=C2=A0 =C2=A0 =C2=A0 pc +=3D INST_WORD_SIZE;
>> +=C2=A0 =C2=A0 =C2=A0 insn =3D microblaze_fetch_instruction (pc);<= br> >> +=C2=A0 =C2=A0 =C2=A0 get_insn_microblaze (insn, &isunsignednu= m, &insn_type, &delay_slots);
>> +=C2=A0 =C2=A0 }
>> +
>> +=C2=A0 std::optional<CORE_ADDR> next_pc, branch_or_return_p= c;
>> +
>> +=C2=A0 /* Compute next instruction address - skip delay slots if = any.=C2=A0 */
>> +
>> +=C2=A0 if (insn_type !=3D return_inst)
>> +=C2=A0 =C2=A0 next_pc =3D pc + INST_WORD_SIZE + (delay_slots * IN= ST_WORD_SIZE);
>> +
>> +=C2=A0 microblaze_debug ("single-step insn_type=3D0x%x pc=3D= 0x%lx insn=3D0x%lx\n",
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 insn_type= , pc, insn);
>
> You shouldn't need the trailing \n.=C2=A0 Apply elsewhere too.
>
>> +
>> +=C2=A0 /* Compute target instruction address for branch or return= instruction.=C2=A0 */
>> +=C2=A0 if (insn_type =3D=3D branch_inst || insn_type =3D=3D retur= n_inst)
>> +=C2=A0 =C2=A0 {
>> +=C2=A0 =C2=A0 =C2=A0 int limm;
>> +=C2=A0 =C2=A0 =C2=A0 int lrd, lra, lrb;
>> +=C2=A0 =C2=A0 =C2=A0 long ra, rb;
>> +=C2=A0 =C2=A0 =C2=A0 bool targetvalid;
>> +=C2=A0 =C2=A0 =C2=A0 bool unconditionalbranch;
>
> Declare when first use, where possible (ra and rb).
>
> ra and rb should probably be of the type ULONGEST.
>
>> +
>> +=C2=A0 =C2=A0 =C2=A0 microblaze_decode_insn (insn, &lrd, &= ;lra, &lrb, &limm);
>> +=C2=A0 =C2=A0 =C2=A0 ra =3D regcache_raw_get_unsigned (regcache, = lra);
>> +=C2=A0 =C2=A0 =C2=A0 rb =3D regcache_raw_get_unsigned (regcache, = lrb);
>> +
>> +=C2=A0 =C2=A0 =C2=A0 branch_or_return_pc =3D microblaze_get_targe= t_address (insn, immfound,
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 im= m, pc, ra, rb, &targetvalid, &unconditionalbranch);
>
> Format like this:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 branch_or_return_pc
>=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D microblaze_get_target_address (insn, imm= found,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 imm, = pc, ra, rb, &targetvalid,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &= unconditionalbranch);
>
>> +
>> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug (
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &q= uot;single-step uncondbr=3D%d targetvalid=3D%d target=3D0x%lx\n",
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 un= conditionalbranch, targetvalid,
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 br= anch_or_return_pc.value () );
>
> Format like this:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 microblaze_debug ("single-step uncondb= r=3D%d targetvalid=3D%d target=3D0x%lx",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0unconditionalbranch, targetvalid,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0branch_or_return_pc.value ());
>
>> +
>> +=C2=A0 =C2=A0 =C2=A0 /* Can't reach next address.=C2=A0 */ >> +=C2=A0 =C2=A0 =C2=A0 if (unconditionalbranch)
>> +=C2=A0 =C2=A0 next_pc.reset ();
>> +
>> +=C2=A0 =C2=A0 =C2=A0 /* Can't reach a distinct (not here) tar= get address.=C2=A0 */
>> +=C2=A0 =C2=A0 =C2=A0 if (! targetvalid || branch_or_return_pc =3D= =3D pc ||
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (n= ext_pc && (branch_or_return_pc =3D=3D next_pc)))
>> +=C2=A0 =C2=A0 =C2=A0 branch_or_return_pc.reset ();
>
> Format like this:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Can't reach a distinct (not here) ta= rget address.=C2=A0 */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!targetvalid
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|| branch_or_return_pc =3D=3D pc
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|| (next_pc.has_value () && b= ranch_or_return_pc =3D=3D next_pc))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0branch_or_return_pc.reset ();
>
>
>> +=C2=A0 =C2=A0 } /* if (branch or return instruction).=C2=A0 */ >> +
>> +=C2=A0 /* Create next_pcs vector to return.=C2=A0 */
>> +
>> +=C2=A0 std::vector<CORE_ADDR> next_pcs;
>> +
>> +=C2=A0 if (next_pc)
>
> .has_value ()
>
>> +=C2=A0 =C2=A0 {
>> +=C2=A0 =C2=A0 =C2=A0 next_pcs.push_back (next_pc.value () );
>
> We typically use `*next_pc` to access the value (apply elsewhere too).=
>
> Remove the space before closing parenthesis (apply elsewhere too).
>
>> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug ("push_back next_pc(0x= %lx)\n", next_pc.value () );
>> +=C2=A0 =C2=A0 }
>> +
>> +=C2=A0 if (branch_or_return_pc)
>> +=C2=A0 =C2=A0 {
>> +=C2=A0 =C2=A0 =C2=A0 next_pcs.push_back ( branch_or_return_pc.val= ue () );
>> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug ("push_back branch_or_= return_pc(0x%lx)\n",
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 br= anch_or_return_pc.value ());
>
> Align the last line properly.
>
> The patch LGTM with those fixed.=C2=A0 Let me know if you need help pu= shing
> the patch.
>

This caused a buildbreaker on arm-linux with --enable-targets=3Dall and --enable-64-bit-bfd.


reverted commit c6df5d79aac5c4a77c0631= 4fd26c837470360f70

dhanyavaadaaha
gopi


I've filed a PR ( https://sourceware.org/= bugzilla/show_bug.cgi?id=3D33381 ).=C2=A0

Thanks,
- Tom

> Approved-By: Simon Marchi <simon.marchi@efficios.com>
>
> Simon

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