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Thu, 04 Sep 2025 05:11:23 -0700 (PDT) MIME-Version: 1.0 References: <3bdebc70-e678-44e7-98ec-18c6b23dccca@simark.ca> <93642dcc-4922-4a15-84ae-2404e9d54a17@simark.ca> In-Reply-To: <93642dcc-4922-4a15-84ae-2404e9d54a17@simark.ca> From: Gopi Kumar Bulusu Date: Thu, 4 Sep 2025 17:10:49 +0530 X-Gm-Features: Ac12FXw3dhuPAITrdrvUD3M9947HPX6bW7juJwYZN8jHnFnIKqiPym1ajx2WWVM Message-ID: Subject: Re: [PATCH v2 ] MicroBlaze: Add microblaze_get_next_pcs To: Simon Marchi Cc: gdb-patches@sourceware.org, Michael Eager Content-Type: multipart/alternative; boundary="000000000000af47be063df89eeb" X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org --000000000000af47be063df89eeb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Sep 3, 2025 at 11:27=E2=80=AFPM Simon Marchi wro= te: > On 9/2/25 8:27 AM, Gopi Kumar Bulusu wrote: > > From 7f2bacc6fffa6830991da36c2044431237bacba1 Mon Sep 17 00:00:00 2001 > > From: Gopi Kumar Bulusu > > Date: Tue, 12 Aug 2025 09:42:48 +0530 > > Subject: [PATCH v2] MicroBlaze: Add microblaze_get_next_pcs > > > > This patch enables software single stepping for gdbserver target > > > > * gdb/microblaze-tdep.c: Add microblaze_get_next_pcs > > > > Signed-off-by: David Holsgrove > > Signed-off-by: Nathan Rossi > > Signed-off-by: Mahesh Bodapati > > Signed-off-by: Gopi Kumar Bulusu > > --- > > gdb/microblaze-tdep.c | 91 +++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 91 insertions(+) > > > > diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c > > index 7b58220871c..cacec8ba186 100644 > > --- a/gdb/microblaze-tdep.c > > +++ b/gdb/microblaze-tdep.c > > @@ -590,6 +590,95 @@ microblaze_stabs_argument_has_addr (struct gdbarch > *gdbarch, struct type *type) > > return (type->length () =3D=3D 16); > > } > > > > +/* Return next pc values : next in sequence and/or branch/return > target. */ > > + > > +static std::vector > > +microblaze_get_next_pcs (regcache *regcache) > > +{ > > + CORE_ADDR pc =3D regcache_read_pc (regcache); > > + long insn =3D microblaze_fetch_instruction (pc); > > + > > + enum microblaze_instr_type insn_type; > > + short delay_slots; > > + bool isunsignednum; > > + > > + /* If the current instruction is an imm, look at the inst after. */ > > + > > + get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots)= ; > > + > > + int imm; > > + bool immfound =3D false; > > + > > + if (insn_type =3D=3D immediate_inst) > > + { > > + int rd, ra, rb; > > + immfound =3D true; > > + microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); > > + pc +=3D INST_WORD_SIZE; > > + insn =3D microblaze_fetch_instruction (pc); > > + get_insn_microblaze (insn, &isunsignednum, &insn_type, > &delay_slots); > > + } > > + > > + std::optional next_pc, branch_or_return_pc; > > + > > + /* Compute next instruction address - skip delay slots if any. */ > > + > > + if (insn_type !=3D return_inst) > > + next_pc =3D pc + INST_WORD_SIZE + (delay_slots * INST_WORD_SIZE); > > + > > + microblaze_debug ("single-step insn_type=3D0x%x pc=3D0x%lx insn=3D0x= %lx\n", > > + insn_type, pc, insn); > > You shouldn't need the trailing \n. Apply elsewhere too. > ok. > > > + > > + /* Compute target instruction address for branch or return > instruction. */ > > + if (insn_type =3D=3D branch_inst || insn_type =3D=3D return_inst) > > + { > > + int limm; > > + int lrd, lra, lrb; > > + long ra, rb; > > + bool targetvalid; > > + bool unconditionalbranch; > > Declare when first use, where possible (ra and rb). > > ra and rb should probably be of the type ULONGEST. > > Will check. > > + > > + microblaze_decode_insn (insn, &lrd, &lra, &lrb, &limm); > > + ra =3D regcache_raw_get_unsigned (regcache, lra); > > + rb =3D regcache_raw_get_unsigned (regcache, lrb); > > + > > + branch_or_return_pc =3D microblaze_get_target_address (insn, > immfound, > > + imm, pc, ra, rb, &targetvalid, &unconditionalbranch= ); > > Format like this: > > branch_or_return_pc > =3D microblaze_get_target_address (insn, immfound, > imm, pc, ra, rb, &targetvalid, > &unconditionalbranch); > ok > > > + > > + microblaze_debug ( > > + "single-step uncondbr=3D%d targetvalid=3D%d > target=3D0x%lx\n", > > + unconditionalbranch, targetvalid, > > + branch_or_return_pc.value () ); > > Format like this: > > microblaze_debug ("single-step uncondbr=3D%d targetvalid=3D%d > target=3D0x%lx", > unconditionalbranch, targetvalid, > branch_or_return_pc.value ()); > ok > > > + > > + /* Can't reach next address. */ > > + if (unconditionalbranch) > > + next_pc.reset (); > > + > > + /* Can't reach a distinct (not here) target address. */ > > + if (! targetvalid || branch_or_return_pc =3D=3D pc || > > + (next_pc && (branch_or_return_pc =3D=3D next_pc))) > > + branch_or_return_pc.reset (); > > Format like this: > > /* Can't reach a distinct (not here) target address. */ > if (!targetvalid > || branch_or_return_pc =3D=3D pc > || (next_pc.has_value () && branch_or_return_pc =3D=3D next_pc)= ) > branch_or_return_pc.reset (); > > ok > > > + } /* if (branch or return instruction). */ > > + > > + /* Create next_pcs vector to return. */ > > + > > + std::vector next_pcs; > > + > > + if (next_pc) > > .has_value () > > ok > > + { > > + next_pcs.push_back (next_pc.value () ); > > We typically use `*next_pc` to access the value (apply elsewhere too). > ok > > Remove the space before closing parenthesis (apply elsewhere too). > ok > > > + microblaze_debug ("push_back next_pc(0x%lx)\n", next_pc.value () > ); > > + } > > + > > + if (branch_or_return_pc) > > + { > > + next_pcs.push_back ( branch_or_return_pc.value () ); > > + microblaze_debug ("push_back branch_or_return_pc(0x%lx)\n", > > + branch_or_return_pc.value ()); > > Align the last line properly. > > ok > The patch LGTM with those fixed. Let me know if you need help pushing > the patch. > > Approved-By: Simon Marchi > Thank you for the review. I will try to push the patch after addressing the above. I will ask for help if needed. dhanyavaadaaha gopi > Simon > --000000000000af47be063df89eeb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
=C2=A0
On Wed, Sep 3= , 2025 at 11:27=E2=80=AFPM Simon Marchi <simark@simark.ca> wrote:
On 9/2/25 8:27 AM, Gopi Kumar Bulusu wrote:
> From 7f2bacc6fffa6830991da36c2044431237bacba1 Mon Sep 17 00:00:00 2001=
> From: Gopi Kumar Bulusu <gopi@sankhya.com>
> Date: Tue, 12 Aug 2025 09:42:48 +0530
> Subject: [PATCH v2] MicroBlaze: Add microblaze_get_next_pcs
>
> This patch enables software single stepping for gdbserver target
>
> * gdb/microblaze-tdep.c: Add microblaze_get_next_pcs
>
> Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
> Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
> Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
> Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
> ---
>=C2=A0 gdb/microblaze-tdep.c | 91 +++++++++++++++++++++++++++++++++++++= ++++++
>=C2=A0 1 file changed, 91 insertions(+)
>
> diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
> index 7b58220871c..cacec8ba186 100644
> --- a/gdb/microblaze-tdep.c
> +++ b/gdb/microblaze-tdep.c
> @@ -590,6 +590,95 @@ microblaze_stabs_argument_has_addr (struct gdbarc= h *gdbarch, struct type *type)
>=C2=A0 =C2=A0 return (type->length () =3D=3D 16);
>=C2=A0 }
>=C2=A0
> +/* Return next pc values : next in sequence and/or branch/return targ= et.=C2=A0 */
> +
> +static std::vector<CORE_ADDR>
> +microblaze_get_next_pcs (regcache *regcache)
> +{
> +=C2=A0 CORE_ADDR pc =3D regcache_read_pc (regcache);
> +=C2=A0 long insn =3D microblaze_fetch_instruction (pc);
> +
> +=C2=A0 enum microblaze_instr_type insn_type;
> +=C2=A0 short delay_slots;
> +=C2=A0 bool isunsignednum;
> +
> +=C2=A0 /* If the current instruction is an imm, look at the inst afte= r.=C2=A0 */
> +
> +=C2=A0 get_insn_microblaze (insn, &isunsignednum, &insn_type,= &delay_slots);
> +
> +=C2=A0 int imm;
> +=C2=A0 bool immfound =3D false;
> +
> +=C2=A0 if (insn_type =3D=3D immediate_inst)
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 int rd, ra, rb;
> +=C2=A0 =C2=A0 =C2=A0 immfound =3D true;
> +=C2=A0 =C2=A0 =C2=A0 microblaze_decode_insn (insn, &rd, &ra, = &rb, &imm);
> +=C2=A0 =C2=A0 =C2=A0 pc +=3D INST_WORD_SIZE;
> +=C2=A0 =C2=A0 =C2=A0 insn =3D microblaze_fetch_instruction (pc);
> +=C2=A0 =C2=A0 =C2=A0 get_insn_microblaze (insn, &isunsignednum, &= amp;insn_type, &delay_slots);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 std::optional<CORE_ADDR> next_pc, branch_or_return_pc; > +
> +=C2=A0 /* Compute next instruction address - skip delay slots if any.= =C2=A0 */
> +
> +=C2=A0 if (insn_type !=3D return_inst)
> +=C2=A0 =C2=A0 next_pc =3D pc + INST_WORD_SIZE + (delay_slots * INST_W= ORD_SIZE);
> +
> +=C2=A0 microblaze_debug ("single-step insn_type=3D0x%x pc=3D0x%l= x insn=3D0x%lx\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0insn_ty= pe, pc, insn);

You shouldn't need the trailing \n.=C2=A0 Apply elsewhere too.

ok.
=C2=A0

> +
> +=C2=A0 /* Compute target instruction address for branch or return ins= truction.=C2=A0 */
> +=C2=A0 if (insn_type =3D=3D branch_inst || insn_type =3D=3D return_in= st)
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 int limm;
> +=C2=A0 =C2=A0 =C2=A0 int lrd, lra, lrb;
> +=C2=A0 =C2=A0 =C2=A0 long ra, rb;
> +=C2=A0 =C2=A0 =C2=A0 bool targetvalid;
> +=C2=A0 =C2=A0 =C2=A0 bool unconditionalbranch;

Declare when first use, where possible (ra and rb).

ra and rb should probably be of the type ULONGEST.


Will check.
=C2=A0
=
> +
> +=C2=A0 =C2=A0 =C2=A0 microblaze_decode_insn (insn, &lrd, &lra= , &lrb, &limm);
> +=C2=A0 =C2=A0 =C2=A0 ra =3D regcache_raw_get_unsigned (regcache, lra)= ;
> +=C2=A0 =C2=A0 =C2=A0 rb =3D regcache_raw_get_unsigned (regcache, lrb)= ;
> +
> +=C2=A0 =C2=A0 =C2=A0 branch_or_return_pc =3D microblaze_get_target_ad= dress (insn, immfound,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= imm, pc, ra, rb, &targetvalid, &unconditionalbranch);

Format like this:

=C2=A0 =C2=A0 =C2=A0 branch_or_return_pc
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D microblaze_get_target_address (insn, immfou= nd,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0im= m, pc, ra, rb, &targetvalid,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&a= mp;unconditionalbranch);

ok=C2=A0
<= /div>

> +
> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug (
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= "single-step uncondbr=3D%d targetvalid=3D%d target=3D0x%lx\n", > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= unconditionalbranch, targetvalid,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= branch_or_return_pc.value () );

Format like this:

=C2=A0 =C2=A0 =C2=A0 microblaze_debug ("single-step uncondbr=3D%d targ= etvalid=3D%d target=3D0x%lx",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 unconditionalbranch, targetvalid,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 branch_or_return_pc.value ());

ok
=C2=A0

> +
> +=C2=A0 =C2=A0 =C2=A0 /* Can't reach next address.=C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0 if (unconditionalbranch)
> +=C2=A0 =C2=A0 =C2=A0next_pc.reset ();
> +
> +=C2=A0 =C2=A0 =C2=A0 /* Can't reach a distinct (not here) target = address.=C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0 if (! targetvalid || branch_or_return_pc =3D=3D = pc ||
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= (next_pc && (branch_or_return_pc =3D=3D next_pc)))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0branch_or_return_pc.reset ();

Format like this:

=C2=A0 =C2=A0 =C2=A0 /* Can't reach a distinct (not here) target addres= s.=C2=A0 */
=C2=A0 =C2=A0 =C2=A0 if (!targetvalid
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 || branch_or_return_pc =3D=3D pc
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 || (next_pc.has_value () && bran= ch_or_return_pc =3D=3D next_pc))
=C2=A0 =C2=A0 =C2=A0 =C2=A0 branch_or_return_pc.reset ();


ok
=C2=A0

> +=C2=A0 =C2=A0 } /* if (branch or return instruction).=C2=A0 */
> +
> +=C2=A0 /* Create next_pcs vector to return.=C2=A0 */
> +
> +=C2=A0 std::vector<CORE_ADDR> next_pcs;
> +
> +=C2=A0 if (next_pc)

.has_value ()


ok
=C2=A0
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 next_pcs.push_back (next_pc.value () );

We typically use `*next_pc` to access the value (apply elsewhere too).
<= /blockquote>

ok
=C2=A0

Remove the space before closing parenthesis (apply elsewhere too).

ok

> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug ("push_back next_pc(0x%lx)= \n", next_pc.value () );
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 if (branch_or_return_pc)
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 next_pcs.push_back ( branch_or_return_pc.value (= ) );
> +=C2=A0 =C2=A0 =C2=A0 microblaze_debug ("push_back branch_or_retu= rn_pc(0x%lx)\n",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= branch_or_return_pc.value ());

Align the last line properly.


ok
=C2=A0
The patch LGTM with those fixed.=C2=A0 Let me know if you need help pushing=
the patch.

Approved-By: Simon Marchi <simon.marchi@efficios.com>
Thank you for the review. I will try to push the patch after a= ddressing the above.
I will ask for help if needed.

dhanyavaadaaha
gopi


Simon
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