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Date: Mon, 19 Dec 2011 06:26:00 -0000
Message-ID: <CAK1A=4yOqa7vcAgZHTkjohH9U_N8ss_XL4frEJ3=ydbuQ1zpLQ@mail.gmail.com>
Subject: Re: [PATCH] arm reversible : <phase_2_complete>
From: oza Pawandeep <oza.pawandeep@gmail.com>
To: Tom Tromey <tromey@redhat.com>
Cc: =?ISO-8859-1?Q?Petr_Hluz=EDn?= <petr.hluzin@gmail.com>, 	paawan oza <paawan1982@yahoo.com>, 	"gdb-patches@sourceware.org" <gdb-patches@sourceware.org>, 	chandra krishnappa <chandra_roadking@yahoo.com>, Yao Qi <yao@codesourcery.com>
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Hi Tom,

I suppose you have no more comment for the latest patch, and rest of
the comments are closed
too. Changelog is attached too.

please let me know the next step;

Regards,
Oza.


On Mon, Dec 5, 2011 at 9:05 PM, oza Pawandeep <oza.pawandeep@gmail.com> wro=
te:
> Hi Yao,
>
> here is the latest patch with Changelog comment fixed.
>
> diff -urN arm_orig/ChangeLog arm_new/ChangeLog
> --- arm_orig/ChangeLog =A02011-12-03 18:05:04.000000000 +0530
> +++ arm_new/ChangeLog =A0 2011-12-04 23:36:50.000000000 +0530
> @@ -1,3 +1,37 @@
> +2011-12-03 =A0Oza Pawandeep =A0 <oza.pawandeep@gmail.com>
> +
> + =A0 =A0 =A0 * arm-linux-tdep.c (arm_linux_init_abi): Call
> + =A0 =A0 =A0 set_gdbarch_process_record.
> + =A0 =A0 =A0 Initialize `arm_swi_record' field.
> +
> + =A0 =A0 =A0 * arm-tdep.c (arm_process_record): New function.
> + =A0 =A0 =A0 (deallocate_reg_mem): New function.
> + =A0 =A0 =A0 (decode_insn): New function.
> + =A0 =A0 =A0 (thumb_record_branch): New function.
> + =A0 =A0 =A0 (thumb_record_ldm_stm_swi(): New function.
> + =A0 =A0 =A0 (thumb_record_misc): New function.
> + =A0 =A0 =A0 (thumb_record_ld_st_stack): New function.
> + =A0 =A0 =A0 (thumb_record_ld_st_imm_offset): New function.
> + =A0 =A0 =A0 (thumb_record_ld_st_reg_offset(): New function.
> + =A0 =A0 =A0 (thumb_record_add_sub_cmp_mov): New function.
> + =A0 =A0 =A0 (thumb_record_shift_add_sub): New function.
> + =A0 =A0 =A0 (arm_record_coproc_data_proc): New function.
> + =A0 =A0 =A0 (arm_record_coproc): New function.
> + =A0 =A0 =A0 (arm_record_b_bl): New function.
> + =A0 =A0 =A0 (arm_record_ld_st_multiple): New function.
> + =A0 =A0 =A0 (arm_record_ld_st_reg_offset): New function.
> + =A0 =A0 =A0 (arm_record_ld_st_imm_offset): New function.
> + =A0 =A0 =A0 (arm_record_data_proc_imm): New function.
> + =A0 =A0 =A0 (arm_record_data_proc_misc_ld_str): New function.
> + =A0 =A0 =A0 (arm_record_extension_space): New function.
> + =A0 =A0 =A0 (arm_record_strx): New function.
> + =A0 =A0 =A0 (sbo_sbz): New function.
> + =A0 =A0 =A0 (struct insn_decode_record): New structure for arm insn rec=
ord.
> + =A0 =A0 =A0 (REG_ALLOC): New macro for reg allocations.
> + =A0 =A0 =A0 (MEM_ALLOC): New macro for memory allocations.
> +
> + =A0 =A0 =A0 * arm-tdep.h (struct gdbarch_tdep): New field 'arm_swi_reco=
rd'
> +
> =A02011-11-09 =A0Roland McGrath =A0<mcgrathr@google.com>
>
> =A0 =A0 =A0 =A0* configure.ac: Add tool checks for READELF and READELF_FO=
R_TARGET.
> diff -urN arm_orig/arm-linux-tdep.c arm_new/arm-linux-tdep.c
> --- arm_orig/arm-linux-tdep.c =A0 2011-12-03 18:06:39.000000000 +0530
> +++ arm_new/arm-linux-tdep.c =A0 =A02011-12-03 19:28:27.000000000 +0530
> @@ -1148,8 +1148,14 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 simple_displaced_step_free_closure);
> =A0 set_gdbarch_displaced_step_location (gdbarch, displaced_step_at_entry=
_point);
>
> + =A0/* Reversible debugging, process record. =A0*/
> + =A0set_gdbarch_process_record (gdbarch, arm_process_record);
> +
>
> =A0 tdep->syscall_next_pc =3D arm_linux_syscall_next_pc;
> +
> + =A0/* Syscall record. =A0*/
> + =A0tdep->arm_swi_record =3D NULL;
> =A0}
>
> =A0/* Provide a prototype to silence -Wmissing-prototypes. =A0*/
> diff -urN arm_orig/arm-tdep.c arm_new/arm-tdep.c
> --- arm_orig/arm-tdep.c 2011-12-03 20:05:03.000000000 +0530
> +++ arm_new/arm-tdep.c =A02011-12-04 22:04:36.000000000 +0530
> @@ -55,6 +55,8 @@
> =A0#include "gdb_assert.h"
> =A0#include "vec.h"
>
> +#include "record.h"
> +
> =A0#include "features/arm-with-m.c"
> =A0#include "features/arm-with-iwmmxt.c"
> =A0#include "features/arm-with-vfpv2.c"
> @@ -10175,3 +10177,2063 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 NULL, /* FIXME: i18n:=
 "ARM debugging is %s. =A0*/
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 &setdebuglist, &showd=
ebuglist);
> =A0}
> +
> +/* ARM-reversible process record data structures. =A0*/
> +
> +#define ARM_INSN_SIZE_BYTES 4
> +#define THUMB_INSN_SIZE_BYTES 2
> +#define THUMB2_INSN_SIZE_BYTES 4
> +
> +
> +#define INSN_S_L_BIT_NUM 20
> +
> +#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
> + =A0 =A0 =A0 =A0do =A0\
> + =A0 =A0 =A0 =A0 =A0{ \
> + =A0 =A0 =A0 =A0 =A0 =A0unsigned int reg_len =3D LENGTH; \
> + =A0 =A0 =A0 =A0 =A0 =A0if (reg_len) \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{ \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0REGS =3D XNEWVEC (uint32_t, reg_len); \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0memcpy(&REGS[0], &RECORD_BUF[0], sizeof(=
uint32_t)*LENGTH); \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0} \
> + =A0 =A0 =A0 =A0 =A0} \
> + =A0 =A0 =A0 =A0while (0)
> +
> +#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
> + =A0 =A0 =A0 =A0do =A0\
> + =A0 =A0 =A0 =A0 =A0{ \
> + =A0 =A0 =A0 =A0 =A0 =A0unsigned int mem_len =3D LENGTH; \
> + =A0 =A0 =A0 =A0 =A0 =A0if (mem_len) \
> + =A0 =A0 =A0 =A0 =A0 =A0{ \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0MEMS =3D =A0XNEWVEC (struct arm_mem_r, mem_l=
en); =A0\
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0memcpy(&MEMS->len, &RECORD_BUF[0], \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sizeof(struct arm_mem_r) * LENG=
TH); \
> + =A0 =A0 =A0 =A0 =A0 =A0} \
> + =A0 =A0 =A0 =A0 =A0} \
> + =A0 =A0 =A0 =A0 =A0while (0)
> +
> +/* Checks whether insn is already recorded or yet to be decoded.
> (boolean expression). =A0*/
> +#define INSN_RECORDED(ARM_RECORD) \
> + =A0 =A0 =A0 =A0(0 !=3D (ARM_RECORD)->reg_rec_count || 0 !=3D (ARM_RECOR=
D)->mem_rec_count)
> +
> +/* ARM memory record structure. =A0*/
> +struct arm_mem_r
> +{
> + =A0uint32_t len; =A0 =A0/* Record length. =A0*/
> + =A0CORE_ADDR addr; =A0/* Memory address. =A0*/
> +};
> +
> +/* ARM instruction record contains opcode of current insn
> + =A0 and execution state (before entry to decode_insn()),
> + =A0 contains list of to-be-modified registers and
> + =A0 memory blocks (on return from decode_insn()). =A0*/
> +
> +typedef struct insn_decode_record_t
> +{
> + =A0struct gdbarch *gdbarch;
> + =A0struct regcache *regcache;
> + =A0CORE_ADDR this_addr; =A0 =A0 =A0 =A0 =A0/* Address of the insn being=
 decoded. =A0*/
> + =A0uint32_t arm_insn; =A0 =A0 =A0 =A0 =A0 =A0/* Should accommodate thum=
b. =A0*/
> + =A0uint32_t cond; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Condition code. =A0=
*/
> + =A0uint32_t opcode; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Insn opcode. =A0*/
> + =A0uint32_t decode; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Insn decode bits. =A0=
*/
> + =A0uint32_t mem_rec_count; =A0 =A0 =A0 /* No of mem records. =A0*/
> + =A0uint32_t reg_rec_count; =A0 =A0 =A0 /* No of reg records. =A0*/
> + =A0uint32_t *arm_regs; =A0 =A0 =A0 =A0 =A0 /* Registers to be saved for=
 this record. =A0*/
> + =A0struct arm_mem_r *arm_mems; =A0 /* Memory to be saved for this recor=
d. =A0*/
> +} insn_decode_record;
> +
> +
> +/* Checks ARM SBZ and SBO mandatory fields. =A0*/
> +
> +static int
> +sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
> +{
> + =A0uint32_t ones =3D bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
> +
> + =A0if (!len)
> + =A0 =A0return 1;
> +
> + =A0if (!sbo)
> + =A0 =A0ones =3D ~ones;
> +
> + =A0while (ones)
> + =A0 =A0{
> + =A0 =A0 =A0if (!(ones & sbo))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0return 0;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0ones =3D ones >> 1;
> + =A0 =A0}
> + =A0return 1;
> +}
> +
> +typedef enum
> +{
> + =A0ARM_RECORD_STRH=3D1,
> + =A0ARM_RECORD_STRD
> +} arm_record_strx_t;
> +
> +typedef enum
> +{
> + =A0ARM_RECORD=3D1,
> + =A0THUMB_RECORD,
> + =A0THUMB2_RECORD
> +} record_type_t;
> +
> +
> +static int
> +arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t *record_buf_mem, arm_record_st=
rx_t str_type)
> +{
> +
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> + =A0ULONGEST u_regval[2]=3D {0};
> +
> + =A0uint32_t reg_src1 =3D 0, reg_src2 =3D 0;
> + =A0uint32_t immed_high =3D 0, immed_low =3D 0,offset_8 =3D 0, tgt_mem_a=
ddr =3D 0;
> + =A0uint32_t opcode1 =3D 0;
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24);
> + =A0arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7);
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 20, 24);
> +
> +
> + =A0if (14 =3D=3D arm_insn_r->opcode || 10 =3D=3D arm_insn_r->opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* 1) Handle misc store, immediate offset. =A0*/
> + =A0 =A0 =A0immed_low =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0immed_high =3D bits (arm_insn_r->arm_insn, 8, 11);
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0&u_r=
egval[0]);
> + =A0 =A0 =A0if (ARM_PC_REGNUM =3D=3D reg_src1)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* If R15 was used as Rn, hence current PC+8. =A0*/
> + =A0 =A0 =A0 =A0 =A0u_regval[0] =3D u_regval[0] + 8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0offset_8 =3D (immed_high << 4) | immed_low;
> + =A0 =A0 =A0/* Calculate target store address. =A0*/
> + =A0 =A0 =A0if (14 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] + offset_8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] - offset_8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0if (ARM_RECORD_STRH =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 2;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (ARM_RECORD_STRD =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[3] =3D tgt_mem_addr + 4;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (12 =3D=3D arm_insn_r->opcode || 8 =3D=3D arm_insn_r->opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* 2) Store, register offset. =A0*/
> + =A0 =A0 =A0/* Get Rm. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0=
]);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1=
]);
> + =A0 =A0 =A0if (15 =3D=3D reg_src2)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* If R15 was used as Rn, hence current PC+8. =A0*/
> + =A0 =A0 =A0 =A0 =A0u_regval[0] =3D u_regval[0] + 8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* Calculate target store address, Rn +/- Rm, register offse=
t. =A0*/
> + =A0 =A0 =A0if (12 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] + u_regval[1];
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[1] - u_regval[0];
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0if (ARM_RECORD_STRH =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 2;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (ARM_RECORD_STRD =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[3] =3D tgt_mem_addr + 4;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (11 =3D=3D arm_insn_r->opcode || 15 =3D=3D arm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 || 2 =3D=3D arm_insn_r->opcode =A0|| 6 =3D=3D arm_i=
nsn_r->opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* 3) Store, immediate pre-indexed. =A0*/
> + =A0 =A0 =A0/* 5) Store, immediate post-indexed. =A0*/
> + =A0 =A0 =A0immed_low =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0immed_high =3D bits (arm_insn_r->arm_insn, 8, 11);
> + =A0 =A0 =A0offset_8 =3D (immed_high << 4) | immed_low;
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0=
]);
> + =A0 =A0 =A0/* Calculate target store address, Rn +/- Rm, register offse=
t. =A0*/
> + =A0 =A0 =A0if (15 =3D=3D arm_insn_r->opcode || 6 =3D=3D arm_insn_r->opc=
ode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] + offset_8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] - offset_8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0if (ARM_RECORD_STRH =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 2;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (ARM_RECORD_STRD =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[3] =3D tgt_mem_addr + 4;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* Record Rn also as it changes. =A0*/
> + =A0 =A0 =A0*(record_buf) =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (9 =3D=3D arm_insn_r->opcode || 13 =3D=3D arm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 || 0 =3D=3D arm_insn_r->opcode || 4 =3D=3D arm_insn=
_r->opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* 4) Store, register pre-indexed. =A0*/
> + =A0 =A0 =A0/* 6) Store, register post -indexed. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0=
]);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1=
]);
> + =A0 =A0 =A0/* Calculate target store address, Rn +/- Rm, register offse=
t. =A0*/
> + =A0 =A0 =A0if (13 =3D=3D arm_insn_r->opcode || 4 =3D=3D arm_insn_r->opc=
ode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] + u_regval[1];
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[1] - u_regval[0];
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0if (ARM_RECORD_STRH =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 2;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (ARM_RECORD_STRD =3D=3D str_type)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[3] =3D tgt_mem_addr + 4;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* Record Rn also as it changes. =A0*/
> + =A0 =A0 =A0*(record_buf) =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0return 0;
> +}
> +
> +/* Handling ARM extension space insns. =A0*/
> +
> +static int
> +arm_record_extension_space (insn_decode_record *arm_insn_r)
> +{
> + =A0uint32_t ret =3D 0; =A0/* Return value: -1:record failure ; =A00:suc=
cess =A0*/
> + =A0uint32_t opcode1 =3D 0, opcode2 =3D 0, insn_op1 =3D 0;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> + =A0uint32_t reg_src1 =3D 0;
> + =A0uint32_t immed_high =3D 0, immed_low =3D 0,offset_8 =3D 0, tgt_mem_a=
ddr =3D 0;
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0gdb_assert (!INSN_RECORDED(arm_insn_r));
> + =A0/* Handle unconditional insn extension space. =A0*/
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 20, 27);
> + =A0opcode2 =3D bits (arm_insn_r->arm_insn, 4, 7);
> + =A0if (arm_insn_r->cond)
> + =A0 =A0{
> + =A0 =A0 =A0/* PLD has no affect on architectural state, it just affects
> + =A0 =A0 =A0 =A0 the caches. =A0*/
> + =A0 =A0 =A0if (5 =3D=3D ((opcode1 & 0xE0) >> 5))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* BLX(1) */
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. =
=A0*/
> + =A0 =A0}
> +
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 25, 27);
> + =A0if (3 =3D=3D opcode1 && bit (arm_insn_r->arm_insn, 4))
> + =A0 =A0{
> + =A0 =A0 =A0ret =3D -1;
> + =A0 =A0 =A0/* Undefined instruction on ARM V5; need to handle if later
> + =A0 =A0 =A0 =A0 versions define it. =A0*/
> + =A0 =A0}
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 24, 27);
> + =A0opcode2 =3D bits (arm_insn_r->arm_insn, 4, 7);
> + =A0insn_op1 =3D bits (arm_insn_r->arm_insn, 20, 23);
> +
> + =A0/* Handle arithmetic insn extension space. =A0*/
> + =A0if (!opcode1 && 9 =3D=3D opcode2 && 1 !=3D arm_insn_r->cond
> + =A0 =A0 =A0&& !INSN_RECORDED(arm_insn_r))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle MLA(S) and MUL(S). =A0*/
> + =A0 =A0 =A0if (0 <=3D insn_op1 && 3 >=3D insn_op1)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0}
> + =A0 =A0 =A0else if (4 <=3D insn_op1 && 15 >=3D insn_op1)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0/* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). =A0*/
> + =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0 =A0record_buf[1] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0record_buf[2] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 3;
> + =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 26, 27);
> + =A0opcode2 =3D bits (arm_insn_r->arm_insn, 23, 24);
> + =A0insn_op1 =3D bits (arm_insn_r->arm_insn, 21, 22);
> +
> + =A0/* Handle control insn extension space. =A0*/
> +
> + =A0if (!opcode1 && 2 =3D=3D opcode2 && !bit (arm_insn_r->arm_insn, 20)
> + =A0 =A0 =A0&& 1 !=3D arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
> + =A0 =A0{
> + =A0 =A0 =A0if (!bit (arm_insn_r->arm_insn,25))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (!bits (arm_insn_r->arm_insn, 4, 7))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if ((0 =3D=3D insn_op1) || (2 =3D=3D insn_op=
1))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* MRS. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->=
arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (1 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* CSPR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (3 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SPSR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* We need to get SPSR value, which =
is yet to be done. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record=
 does not support "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 "instruction =A00x%0x at address %s.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 arm_insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 paddress (arm_insn_r->gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 arm_insn_r->this_addr));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return -1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if (1 =3D=3D bits (arm_insn_r->arm_insn, 4, 7))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if (1 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* BX. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (3 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* CLZ. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->=
arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if (3 =3D=3D bits (arm_insn_r->arm_insn, 4, 7))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* BLX. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if (5 =3D=3D bits (arm_insn_r->arm_insn, 4, 7))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* QADD, QSUB, QDADD, QDSUB */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D bits (arm_insn_r->arm_insn=
, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if (7 =3D=3D bits (arm_insn_r->arm_insn, 4, 7))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* BKPT. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Save SPSR also;how? =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record does no=
t support "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"ins=
truction 0x%0x at address %s.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_=
insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0paddress (arm_insn_r->gdbarch, arm_i=
nsn_r->this_addr));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0return -1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if(8 =3D=3D bits (arm_insn_r->arm_insn, 4, 7)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 10 =3D=3D bits (arm_insn_r->arm_i=
nsn, 4, 7)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 12 =3D=3D bits (arm_insn_r->arm_i=
nsn, 4, 7)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 14 =3D=3D bits (arm_insn_r->arm_i=
nsn, 4, 7)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 )
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if (0 =3D=3D insn_op1 || 1 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SMLA<x><y>, SMLAW<y>, SMULW<y>. =
=A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* We dont do optimization for SMULW=
<y> where we
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 need only Rd. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->=
arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (2 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SMLAL<x><y>. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->=
arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D bits (arm_insn_r->=
arm_insn, 16, 19);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (3 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SMUL<x><y>. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->=
arm_insn, 12, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* MSR : immediate form. =A0*/
> + =A0 =A0 =A0 =A0 =A0if (1 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* CSPR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else if (3 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SPSR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* we need to get SPSR value, which is yet t=
o be done =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record does no=
t support "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "in=
struction 0x%0x at address %s.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
arm_insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
paddress (arm_insn_r->gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
arm_insn_r->this_addr));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0return -1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 25, 27);
> + =A0opcode2 =3D bits (arm_insn_r->arm_insn, 20, 24);
> + =A0insn_op1 =3D bits (arm_insn_r->arm_insn, 5, 6);
> +
> + =A0/* Handle load/store insn extension space. =A0*/
> +
> + =A0if (!opcode1 && bit (arm_insn_r->arm_insn, 7)
> + =A0 =A0 =A0&& bit (arm_insn_r->arm_insn, 4) && 1 !=3D arm_insn_r->cond
> + =A0 =A0 =A0&& !INSN_RECORDED(arm_insn_r))
> + =A0 =A0{
> + =A0 =A0 =A0/* SWP/SWPB. =A0*/
> + =A0 =A0 =A0if (0 =3D=3D insn_op1)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* These insn, changes register and memory as well. =
=A0*/
> + =A0 =A0 =A0 =A0 =A0/* SWP or SWPB insn. =A0*/
> + =A0 =A0 =A0 =A0 =A0/* Get memory address given by Rn. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_=
regval);
> + =A0 =A0 =A0 =A0 =A0/* SWP insn ?, swaps word. =A0*/
> + =A0 =A0 =A0 =A0 =A0if (8 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* SWPB insn, swaps only byte. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D u_regval;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (1 =3D=3D insn_op1 && !bit (arm_insn_r->arm_insn, 20=
))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* STRH. =A0*/
> + =A0 =A0 =A0 =A0 =A0arm_record_strx(arm_insn_r, &record_buf[0], &record_=
buf_mem[0],
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ARM_RECORD_STRH);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (2 =3D=3D insn_op1 && !bit (arm_insn_r->arm_insn, 20=
))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* LDRD. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D record_buf[0] + 1;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (3 =3D=3D insn_op1 && !bit (arm_insn_r->arm_insn, 20=
))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* STRD. =A0*/
> + =A0 =A0 =A0 =A0 =A0arm_record_strx(arm_insn_r, &record_buf[0], &record_=
buf_mem[0],
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ARM_RECORD_STRD);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <=3D 3)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* LDRH, LDRSB, LDRSH. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> +
> + =A0 =A0}
> +
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 23, 27);
> + =A0if (24 =3D=3D opcode1 && bit (arm_insn_r->arm_insn, 21)
> + =A0 =A0 =A0&& !INSN_RECORDED(arm_insn_r))
> + =A0 =A0{
> + =A0 =A0 =A0ret =3D -1;
> + =A0 =A0 =A0/* Handle coprocessor insn extension space. =A0*/
> + =A0 =A0}
> +
> + =A0/* To be done for ARMv5 and later; as of now we return -1. =A0*/
> + =A0if (-1 =3D=3D ret)
> + =A0 =A0printf_unfiltered (_("Process record does not support instructio=
n x%0x "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "at address %s.\n"),arm=
_insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddress (arm_insn_r->g=
dbarch,
> arm_insn_r->this_addr));
> +
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> +
> + =A0return ret;
> +}
> +
> +/* Handling opcode 000 insns. =A0*/
> +
> +static int
> +arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> + =A0ULONGEST u_regval[2] =3D {0};
> +
> + =A0uint32_t reg_src1 =3D 0, reg_src2 =3D 0, reg_dest =3D 0;
> + =A0uint32_t immed_high =3D 0, immed_low =3D 0, offset_8 =3D 0, tgt_mem_=
addr =3D 0;
> + =A0uint32_t opcode1 =3D 0;
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24);
> + =A0arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7);
> + =A0opcode1 =3D bits (arm_insn_r->arm_insn, 20, 24);
> +
> + =A0/* Data processing insn /multiply insn. =A0*/
> + =A0if (9 =3D=3D arm_insn_r->decode
> + =A0 =A0 =A0&& ((4 <=3D arm_insn_r->opcode && 7 >=3D arm_insn_r->opcode)
> + =A0 =A0 =A0|| =A0(0 =3D=3D arm_insn_r->opcode || 1 =3D=3D arm_insn_r->o=
pcode)))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle multiply instructions. =A0*/
> + =A0 =A0 =A0/* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. =A0*/
> + =A0 =A0 =A0 =A0if (0 =3D=3D arm_insn_r->opcode || 1 =3D=3D arm_insn_r->=
opcode)
> + =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0/* Handle MLA and MUL. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 16=
, 19);
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0else if (4 <=3D arm_insn_r->opcode && 7 >=3D arm_insn_r-=
>opcode)
> + =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0/* Handle SMLAL, SMULL, UMLAL, UMULL. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 16=
, 19);
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf[1] =3D bits (arm_insn_r->arm_insn, 12=
, 15);
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf[2] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 3;
> + =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
> + =A0 =A0 =A0 =A0 =A0 && (11 =3D=3D arm_insn_r->decode || 13 =3D=3D arm_i=
nsn_r->decode))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle misc load insns, as 20th bit =A0(L =3D 1). =A0*/
> + =A0 =A0 =A0/* LDR insn has a capability to do branching, if
> + =A0 =A0 =A0 =A0 MOV LR, PC is precceded by LDR insn having Rn as R15
> + =A0 =A0 =A0 =A0 in that case, it emulates branch and link insn, and hen=
ce we
> + =A0 =A0 =A0 =A0 need to save CSPR and PC as well. I am not sure this is=
 right
> + =A0 =A0 =A0 =A0 place; as opcode =3D 010 LDR insn make this happen, if =
R15 was
> + =A0 =A0 =A0 =A0 used. =A0*/
> + =A0 =A0 =A0reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0if (15 !=3D reg_dest)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_dest;
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if ((9 =3D=3D arm_insn_r->opcode || 11 =3D=3D arm_insn_r->opcod=
e)
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
> + =A0 =A0 =A0 =A0 =A0 && 2 =3D=3D bits (arm_insn_r->arm_insn, 20, 21))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle MSR insn. =A0*/
> + =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* CSPR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* SPSR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0/* How to read SPSR value? =A0*/
> + =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record does not suppor=
t instruction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"0x%0x at addres=
s %s.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->arm_=
insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0paddress (arm_insn_r->gd=
barch, arm_insn_r->this_addr));
> + =A0 =A0 =A0 =A0 =A0return -1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (9 =3D=3D arm_insn_r->decode
> + =A0 =A0 =A0 =A0 =A0 && (8 =3D=3D arm_insn_r->opcode || 10 =3D=3D arm_in=
sn_r->opcode)
> + =A0 =A0 =A0 =A0 =A0 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handling SWP, SWPB. =A0*/
> + =A0 =A0 =A0/* These insn, changes register and memory as well. =A0*/
> + =A0 =A0 =A0/* SWP or SWPB insn. =A0*/
> +
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0=
]);
> + =A0 =A0 =A0/* SWP insn ?, swaps word. =A0*/
> + =A0 =A0 =A0if (8 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* SWPB insn, swaps only byte. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf_mem[1] =3D u_regval[0];
> + =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (3 =3D=3D arm_insn_r->decode && 0x12 =3D=3D opcode1
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle BLX, branch and link/exchange. =A0*/
> + =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0/* Branch is chosen by setting T bit of CSPR, bitp[0] of=
 Rm,
> + =A0 =A0 =A0 =A0 =A0 and R14 stores the return address. =A0*/
> + =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (7 =3D=3D arm_insn_r->decode && 0x12 =3D=3D opcode1)
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle enhanced software breakpoint insn, BKPT. =A0*/
> + =A0 =A0 =A0/* CPSR is changed to be executed in ARM state, =A0disabling=
 normal
> + =A0 =A0 =A0 =A0 interrupts, entering abort mode. =A0*/
> + =A0 =A0 =A0/* According to high vector configuration PC is set. =A0*/
> + =A0 =A0 =A0/* user hit breakpoint and type reverse, in
> + =A0 =A0 =A0 =A0 that case, we need to go back with previous CPSR and
> + =A0 =A0 =A0 =A0 Program Counter. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> +
> + =A0 =A0 =A0/* Save SPSR also; how? =A0*/
> + =A0 =A0 =A0printf_unfiltered (_("Process record does not support instru=
ction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0x%0x at address %=
s.\n"),arm_insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddress (arm_insn_=
r->gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 arm_insn_r->this_ad=
dr));
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> + =A0else if (11 =3D=3D arm_insn_r->decode
> + =A0 =A0 =A0 =A0 =A0 && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
> + =A0{
> + =A0 =A0/* Handle enhanced store insns and DSP insns (e.g. LDRD). =A0*/
> +
> + =A0 =A0/* Handle str(x) insn */
> + =A0 =A0arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ARM_RECORD_STRH);
> + =A0}
> + =A0else if (1 =3D=3D arm_insn_r->decode && 0x12 =3D=3D opcode1
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle BX, branch and link/exchange. =A0*/
> + =A0 =A0 =A0/* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm.=
 =A0*/
> + =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (1 =3D=3D arm_insn_r->decode && 0x16 =3D=3D opcode1
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
> + =A0 =A0{
> + =A0 =A0 =A0/* Count leading zeros: CLZ. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
> + =A0 =A0 =A0 =A0 =A0 && (8 =3D=3D arm_insn_r->opcode || 10 =3D=3D arm_in=
sn_r->opcode)
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
> + =A0 =A0 =A0 =A0 =A0 && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
> + =A0 =A0 =A0 =A0 =A0)
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle MRS insn. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (arm_insn_r->opcode <=3D 15)
> + =A0 =A0{
> + =A0 =A0 =A0/* Normal data processing insns. =A0*/
> + =A0 =A0 =A0/* Out of 11 shifter operands mode, all the insn modifies de=
stination
> + =A0 =A0 =A0 =A0 register, which is specified by 13-16 decode. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> + =A0return 0;
> +}
> +
> +/* Handling opcode 001 insns. =A0*/
> +
> +static int
> +arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
> +{
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24);
> + =A0arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7);
> +
> + =A0if ((9 =3D=3D arm_insn_r->opcode || 11 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0&& 2 =3D=3D bits (arm_insn_r->arm_insn, 20, 21)
> + =A0 =A0 =A0&& sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
> + =A0 =A0 )
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle MSR insn. =A0*/
> + =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* CSPR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* SPSR is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (arm_insn_r->opcode <=3D 15)
> + =A0 =A0{
> + =A0 =A0 =A0/* Normal data processing insns. =A0*/
> + =A0 =A0 =A0/* Out of 11 shifter operands mode, all the insn modifies de=
stination
> + =A0 =A0 =A0 =A0 register, which is specified by 13-16 decode. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> + =A0return 0;
> +}
> +
> +/* Handling opcode 010 insns. =A0*/
> +
> +static int
> +arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> +
> + =A0uint32_t reg_src1 =3D 0 , reg_dest =3D 0;
> + =A0uint32_t offset_12 =3D 0, tgt_mem_addr =3D 0;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24);
> + =A0arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7);
> +
> + =A0if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
> + =A0 =A0{
> + =A0 =A0 =A0reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0/* LDR insn has a capability to do branching, if
> + =A0 =A0 =A0 =A0 MOV LR, PC is precedded by LDR insn having Rn as R15
> + =A0 =A0 =A0 =A0 in that case, it emulates branch and link insn, and hen=
ce we
> + =A0 =A0 =A0 =A0 need to save CSPR and PC as well. =A0*/
> + =A0 =A0 =A0if (ARM_PC_REGNUM !=3D reg_dest)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_dest;
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0/* Store, immediate offset, immediate pre-indexed,
> + =A0 =A0 =A0 =A0 immediate post-indexed. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0offset_12 =3D bits (arm_insn_r->arm_insn, 0, 11);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
> + =A0 =A0 =A0/* U =3D=3D 1 */
> + =A0 =A0 =A0if (bit (arm_insn_r->arm_insn, 23))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval + offset_12;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval - offset_12;
> + =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0switch (arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 8:
> + =A0 =A0 =A0 =A0 =A0case 12:
> + =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 9:
> + =A0 =A0 =A0 =A0 =A0case 13:
> + =A0 =A0 =A0 =A0 =A0/* STRT. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 1:
> + =A0 =A0 =A0 =A0 =A0case 5:
> + =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 4:
> + =A0 =A0 =A0 =A0 =A0case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 10:
> + =A0 =A0 =A0 =A0 =A0case 14:
> + =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 11:
> + =A0 =A0 =A0 =A0 =A0case 15:
> + =A0 =A0 =A0 =A0 =A0/* STRBT. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 3:
> + =A0 =A0 =A0 =A0 =A0case 7:
> + =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 2:
> + =A0 =A0 =A0 =A0 =A0case 6:
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1;
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0default:
> + =A0 =A0 =A0 =A0 =A0 =A0gdb_assert_not_reached ("no decoding pattern fou=
nd");
> + =A0 =A0 =A0 =A0 =A0break;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> +
> + =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode || 11 =3D=3D arm_insn_r->opc=
ode
> + =A0 =A0 =A0 =A0 =A0|| 13 =3D=3D arm_insn_r->opcode || 15 =3D=3D arm_ins=
n_r->opcode
> + =A0 =A0 =A0 =A0 =A0|| 0 =3D=3D arm_insn_r->opcode || 2 =3D=3D arm_insn_=
r->opcode
> + =A0 =A0 =A0 =A0 =A0|| 4 =3D=3D arm_insn_r->opcode || 6 =3D=3D arm_insn_=
r->opcode
> + =A0 =A0 =A0 =A0 =A0|| 1 =3D=3D arm_insn_r->opcode || 3 =3D=3D arm_insn_=
r->opcode
> + =A0 =A0 =A0 =A0 =A0|| 5 =3D=3D arm_insn_r->opcode || 7 =3D=3D arm_insn_=
r->opcode
> + =A0 =A0 =A0 =A0 )
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* We are handling pre-indexed mode; post-indexed mo=
de;
> + =A0 =A0 =A0 =A0 =A0 =A0 where Rn is going to be changed. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> + =A0return 0;
> +}
> +
> +/* Handling opcode 011 insns. =A0*/
> +
> +static int
> +arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> +
> + =A0uint32_t shift_imm =3D 0;
> + =A0uint32_t reg_src1 =3D 0, reg_src2 =3D 0, reg_dest =3D 0;
> + =A0uint32_t offset_12 =3D 0, tgt_mem_addr =3D 0;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0LONGEST s_word;
> + =A0ULONGEST u_regval[2];
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24);
> + =A0arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7);
> +
> + =A0/* Handle enhanced store insns and LDRD DSP insn,
> + =A0 =A0 order begins according to addressing modes for store insns
> + =A0 =A0 STRH insn. =A0*/
> +
> + =A0/* LDR or STR? =A0*/
> + =A0if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
> + =A0 =A0{
> + =A0 =A0 =A0reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15);
> + =A0 =A0 =A0/* LDR insn has a capability to do branching, if
> + =A0 =A0 =A0 =A0 MOV LR, PC is precedded by LDR insn having Rn as R15
> + =A0 =A0 =A0 =A0 in that case, it emulates branch and link insn, and hen=
ce we
> + =A0 =A0 =A0 =A0 need to save CSPR and PC as well. =A0*/
> + =A0 =A0 =A0if (15 !=3D reg_dest)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15=
);
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_dest;
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0if (! bits (arm_insn_r->arm_insn, 4, 11))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* Store insn, register offset and register pre-inde=
xed,
> + =A0 =A0 =A0 =A0 =A0 =A0 register post-indexed. =A0*/
> + =A0 =A0 =A0 =A0 =A0/* Get Rm. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0, &u_regval[0]);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0, &u_regval[1]);
> + =A0 =A0 =A0 =A0 =A0if (15 =3D=3D reg_src2)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* If R15 was used as Rn, hence current PC+8=
. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Pre-indexed mode doesnt reach here ; ille=
gal insn. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0u_regval[0] =3D u_regval[0] + 8;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0/* Calculate target store address, Rn +/- Rm, regist=
er offset. =A0*/
> + =A0 =A0 =A0 =A0 =A0/* U =3D=3D 1. =A0*/
> + =A0 =A0 =A0 =A0 =A0if (bit (arm_insn_r->arm_insn, 23))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[0] + u_regval[1];
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[1] - u_regval[0];
> + =A0 =A0 =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0 =A0 =A0switch (arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 8:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 12:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 9:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 13:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRT. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 5:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 4:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 10:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 14:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 11:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 15:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRBT. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 3:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 7:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 2:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 6:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0gdb_assert_not_reached ("no decoding pat=
tern found");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> +
> + =A0 =A0 =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode || 11 =3D=3D arm_ins=
n_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 13 =3D=3D arm_insn_r->opcode || 15 =3D=3D=
 arm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 0 =3D=3D arm_insn_r->opcode || 2 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 4 =3D=3D arm_insn_r->opcode || 6 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 1 =3D=3D arm_insn_r->opcode || 3 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 5 =3D=3D arm_insn_r->opcode || 7 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 )
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Rn is going to be changed in pre-indexed =
mode and
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 post-indexed mode as well. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_src2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* Store insn, scaled register offset; scaled pre-in=
dexed. =A0*/
> + =A0 =A0 =A0 =A0 =A0offset_12 =3D bits (arm_insn_r->arm_insn, 5, 6);
> + =A0 =A0 =A0 =A0 =A0/* Get Rm. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);
> + =A0 =A0 =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0 =A0 =A0/* Get shift_imm. =A0*/
> + =A0 =A0 =A0 =A0 =A0shift_imm =3D bits (arm_insn_r->arm_insn, 7, 11);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_=
regval[0]);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_signed (reg_cache, reg_src1, &s_wo=
rd);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2, &u_=
regval[1]);
> + =A0 =A0 =A0 =A0 =A0/* Offset_12 used as shift. =A0*/
> + =A0 =A0 =A0 =A0 =A0switch (offset_12)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Offset_12 used as index. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D u_regval[0] << shift_imm;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D (!shift_imm)?0:u_regval[0]=
 >> shift_imm;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 2:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (!shift_imm)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (bit (u_regval[0], 31))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D 0xFFFFFFFF;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* This is arithmetic shift. =A0=
*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D s_word >> shift_im=
m;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 3:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (!shift_imm)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_=
cache, ARM_PS_REGNUM,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0&u_regval[1]);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Get C flag value and shift it=
 by 31. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D (((bit (u_regval[1=
], 29)) << 31) \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| (u=
_regval[0]) >> 1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset_12 =3D (u_regval[0] >> sh=
ift_imm) \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| (u_reg=
val[0] <<
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(sizeof(=
uint32_t) - shift_imm));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0gdb_assert_not_reached ("no decoding pat=
tern found");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2, &u_=
regval[1]);
> + =A0 =A0 =A0 =A0 =A0/* bit U set. =A0*/
> + =A0 =A0 =A0 =A0 =A0if (bit (arm_insn_r->arm_insn, 23))
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[1] + offset_12;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tgt_mem_addr =3D u_regval[1] - offset_12;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0 =A0 =A0switch (arm_insn_r->opcode)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 8:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 12:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 9:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 13:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRT. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 5:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STR. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 4:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 10:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 14:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 11:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 15:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRBT. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 3:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 7:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* STRB. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 2:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0case 6:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0gdb_assert_not_reached ("no decoding pat=
tern found");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D tgt_mem_addr;
> + =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D 1;
> +
> + =A0 =A0 =A0 =A0 =A0if (9 =3D=3D arm_insn_r->opcode || 11 =3D=3D arm_ins=
n_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 13 =3D=3D arm_insn_r->opcode || 15 =3D=3D=
 arm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 0 =3D=3D arm_insn_r->opcode || 2 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 4 =3D=3D arm_insn_r->opcode || 6 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 1 =3D=3D arm_insn_r->opcode || 3 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0|| 5 =3D=3D arm_insn_r->opcode || 7 =3D=3D a=
rm_insn_r->opcode
> + =A0 =A0 =A0 =A0 =A0 =A0 )
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Rn is going to be changed in register sca=
led pre-indexed
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mode,and scaled post indexed mode. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_src2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> + =A0return 0;
> +}
> +
> +/* Handling opcode 100 insns. =A0*/
> +
> +static int
> +arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> +
> + =A0uint32_t register_list[16] =3D {0}, register_count =3D 0, register_b=
its =3D 0;
> + =A0uint32_t reg_src1 =3D 0, addr_mode =3D 0, no_of_regs =3D 0;
> + =A0uint32_t start_address =3D 0, index =3D 0;
> + =A0uint32_t record_buf[24], record_buf_mem[48];
> +
> + =A0ULONGEST u_regval[2] =3D {0};
> +
> + =A0/* This mode is exclusively for load and store multiple. =A0*/
> + =A0/* Handle incremenrt after/before and decrment after.before mode;
> + =A0 =A0 Rn is changing depending on W bit, but as of now we store Rn too
> + =A0 =A0 without optimization. =A0*/
> +
> + =A0if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
> + =A0 =A0{
> + =A0 =A0 =A0/* LDM =A0(1,2,3) where LDM =A0(3) changes CPSR too. =A0*/
> +
> + =A0 =A0 =A0if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_=
insn, 22))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0register_bits =3D bits (arm_insn_r->arm_insn, 0, 15);
> + =A0 =A0 =A0 =A0 =A0no_of_regs =3D 15;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0register_bits =3D bits (arm_insn_r->arm_insn, 0, 14);
> + =A0 =A0 =A0 =A0 =A0no_of_regs =3D 14;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0register_list[register_count++] =3D 1;
> + =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0}
> +
> + =A0 =A0 =A0 =A0/* Extra space for Base Register and CPSR; wihtout optim=
ization. =A0*/
> + =A0 =A0 =A0 =A0record_buf[register_count] =3D reg_src1;
> + =A0 =A0 =A0 =A0record_buf[register_count + 1] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0arm_insn_r->reg_rec_count =3D register_count + 2;
> +
> + =A0 =A0 =A0 =A0for (register_count =3D 0; register_count < no_of_regs; =
register_count++)
> + =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0if =A0(register_list[register_count])
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Register_count gives total no of regi=
sters
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0and dually working as reg number. =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[index] =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0index++;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0}
> +
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0/* It handles both STM(1) and STM(2). =A0*/
> + =A0 =A0 =A0addr_mode =3D bits (arm_insn_r->arm_insn, 23, 24);
> +
> + =A0 =A0 =A0register_bits =3D bits (arm_insn_r->arm_insn, 0, 15);
> + =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0=
]);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0 =A0register_count++;
> + =A0 =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0switch (addr_mode)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* Decrement after. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0start_address =3D (u_regval[0]) - (register_coun=
t * 4) + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1]=
 =3D start_address;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2]=
 =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0/* Increment after. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0start_address =3D u_regval[0];
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1]=
 =3D start_address;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2]=
 =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0/* Decrement before. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 2:
> +
> + =A0 =A0 =A0 =A0 =A0 =A0start_address =3D (u_regval[0]) - (register_coun=
t * 4);
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1]=
 =3D start_address;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2]=
 =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0/* Increment before. =A0*/
> + =A0 =A0 =A0 =A0 =A0case 3:
> + =A0 =A0 =A0 =A0 =A0 =A0start_address =3D u_regval[0] + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0arm_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1]=
 =3D start_address;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2]=
 =3D 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0 =A0break;
> +
> + =A0 =A0 =A0 =A0 =A0default:
> + =A0 =A0 =A0 =A0 =A0 =A0gdb_assert_not_reached ("no decoding pattern fou=
nd");
> + =A0 =A0 =A0 =A0 =A0break;
> + =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0/* Base register also changes; based on condition and W bit.=
 =A0*/
> + =A0 =A0 =A0/* We save it anyway without optimization. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> + =A0MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_b=
uf_mem);
> + =A0return 0;
> +}
> +
> +/* Handling opcode 101 insns. =A0*/
> +
> +static int
> +arm_record_b_bl (insn_decode_record *arm_insn_r)
> +{
> + =A0uint32_t record_buf[8];
> +
> + =A0/* Handle B, BL, BLX(1) insns. =A0*/
> + =A0/* B simply branches so we do nothing here. =A0*/
> + =A0/* Note: BLX(1) doesnt fall here but instead it falls into
> + =A0 =A0 extension space. =A0*/
> + =A0if (bit (arm_insn_r->arm_insn, 24))
> + =A0{
> + =A0 =A0record_buf[0] =3D ARM_LR_REGNUM;
> + =A0 =A0arm_insn_r->reg_rec_count =3D 1;
> + =A0}
> +
> + =A0REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_b=
uf);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 110 insns. =A0*/
> +
> +static int
> +arm_record_coproc (insn_decode_record *arm_insn_r)
> +{
> + =A0printf_unfiltered (_("Process record does not support instruction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"0x%0x at address %s.\n"),arm_in=
sn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0paddress (arm_insn_r->gdbarch, a=
rm_insn_r->this_addr));
> +
> + =A0return -1;
> +}
> +
> +/* Handling opcode 111 insns. =A0*/
> +
> +static int
> +arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
> +{
> + =A0struct gdbarch_tdep *tdep =3D gdbarch_tdep (arm_insn_r->gdbarch);
> + =A0struct regcache *reg_cache =3D arm_insn_r->regcache;
> + =A0uint32_t ret =3D 0; /* function return value: -1:record failure ;
> 0:success =A0*/
> +
> + =A0/* Handle SWI insn; system call would be handled over here. =A0*/
> +
> + =A0arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 24, 27);
> + =A0if (15 =3D=3D arm_insn_r->opcode)
> + =A0{
> + =A0 =A0/* Handle arm syscall insn. =A0*/
> + =A0 =A0if (tdep->arm_swi_record !=3D NULL)
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0ret =3D tdep->arm_swi_record(reg_cache);
> + =A0 =A0 =A0}
> + =A0 =A0else
> + =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0printf_unfiltered (_("no syscall record support\n"));
> + =A0 =A0 =A0 =A0ret =3D -1;
> + =A0 =A0 =A0}
> + =A0}
> +
> + =A0printf_unfiltered (_("Process record does not support instruction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"0x%0x at address %s.\n"=
),arm_insn_r->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0paddress (arm_insn_r->gd=
barch, arm_insn_r->this_addr));
> + =A0return ret;
> +}
> +
> +/* Handling opcode 000 insns. =A0*/
> +
> +static int
> +thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
> +{
> + =A0uint32_t record_buf[8];
> + =A0uint32_t reg_src1 =3D 0;
> +
> + =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> +
> + =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0record_buf[1] =3D reg_src1;
> + =A0thumb_insn_r->reg_rec_count =3D 2;
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> +
> + =A0return 0;
> +}
> +
> +
> +/* Handling opcode 001 insns. =A0*/
> +
> +static int
> +thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
> +{
> + =A0uint32_t record_buf[8];
> + =A0uint32_t reg_src1 =3D 0;
> +
> + =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> +
> + =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0record_buf[1] =3D reg_src1;
> + =A0thumb_insn_r->reg_rec_count =3D 2;
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 010 insns. =A0*/
> +
> +static int
> +thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D =A0thumb_insn_r->regcache;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0uint32_t reg_src1 =3D 0, reg_src2 =3D 0;
> + =A0uint32_t opcode1 =3D 0, opcode2 =3D 0, opcode3 =3D 0;
> +
> + =A0ULONGEST u_regval[2] =3D {0};
> +
> + =A0opcode1 =3D bits (thumb_insn_r->arm_insn, 10, 12);
> +
> + =A0if (bit (thumb_insn_r->arm_insn, 12))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle load/store register offset. =A0*/
> + =A0 =A0 =A0opcode2 =3D bits (thumb_insn_r->arm_insn, 9, 10);
> + =A0 =A0 =A0if (opcode2 >=3D 12 && opcode2 <=3D 15)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn,0, 2);
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else if (opcode2 >=3D 8 && opcode2 <=3D 10)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* STR(2), STRB(2), STRH(2) . =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5);
> + =A0 =A0 =A0 =A0 =A0reg_src2 =3D bits (thumb_insn_r->arm_insn, 6, 8);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_=
regval[0]);
> + =A0 =A0 =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src2, &u_=
regval[1]);
> + =A0 =A0 =A0 =A0 =A0if (8 =3D=3D opcode2)
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 4; =A0 =A0/* STR (2). =A0*/
> + =A0 =A0 =A0 =A0 =A0else if (10 =3D=3D opcode2)
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 1; =A0 =A0/* =A0STRB (2). =
=A0*/
> + =A0 =A0 =A0 =A0 =A0else if (9 =3D=3D opcode2)
> + =A0 =A0 =A0 =A0 =A0 =A0record_buf_mem[0] =3D 2; =A0 =A0/* STRH (2). =A0=
*/
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[1] =3D u_regval[0] + u_regval[1];
> + =A0 =A0 =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (bit (thumb_insn_r->arm_insn, 11))
> + =A0 =A0{
> + =A0 =A0 =A0/* Handle load from literal pool. =A0*/
> + =A0 =A0 =A0/* LDR(3). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (opcode1)
> + =A0 =A0{
> + =A0 =A0 =A0opcode2 =3D bits (thumb_insn_r->arm_insn, 8, 9);
> + =A0 =A0 =A0opcode3 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> + =A0 =A0 =A0if ((3 =3D=3D opcode2) && (!opcode3))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* Branch with exchange. =A0*/
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* Format 8; special data processing insns. =A0*/
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> + =A0 =A0 =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0 =A0 =A0record_buf[1] =3D reg_src1;
> + =A0 =A0 =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0/* Format 5; data processing insns. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> + =A0 =A0 =A0if (bit (thumb_insn_r->arm_insn, 7))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0reg_src1 =3D reg_src1 + 8;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0record_buf[1] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 2;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> + =A0MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
> + =A0 =A0 =A0 =A0 =A0 =A0 record_buf_mem);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 001 insns. =A0*/
> +
> +static int
> +thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D thumb_insn_r->regcache;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0uint32_t reg_src1 =3D 0;
> + =A0uint32_t opcode =3D 0, immed_5 =3D 0;
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0opcode =3D bits (thumb_insn_r->arm_insn, 11, 12);
> +
> + =A0if (opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* LDR(1). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0/* STR(1). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5);
> + =A0 =A0 =A0immed_5 =3D bits (thumb_insn_r->arm_insn, 6, 10);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
> + =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0record_buf_mem[1] =3D u_regval + (immed_5 * 4);
> + =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D 1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> + =A0MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
> + =A0 =A0 =A0 =A0 =A0 =A0 record_buf_mem);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 100 insns. =A0*/
> +
> +static int
> +thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D thumb_insn_r->regcache;
> + =A0uint32_t record_buf[8], record_buf_mem[8];
> +
> + =A0uint32_t reg_src1 =3D 0;
> + =A0uint32_t opcode =3D 0, immed_8 =3D 0, immed_5 =3D 0;
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0opcode =3D bits (thumb_insn_r->arm_insn, 11, 12);
> +
> + =A0if (3 =3D=3D opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* LDR(4). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (1 =3D=3D opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* LDRH(1). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2);
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (2 =3D=3D opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* STR(3). =A0*/
> + =A0 =A0 =A0immed_8 =3D bits (thumb_insn_r->arm_insn, 0, 7);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_reg=
val);
> + =A0 =A0 =A0record_buf_mem[0] =3D 4;
> + =A0 =A0 =A0record_buf_mem[1] =3D u_regval + (immed_8 * 4);
> + =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (0 =3D=3D opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* STRH(1). =A0*/
> + =A0 =A0 =A0immed_5 =3D bits (thumb_insn_r->arm_insn, 6, 10);
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
> + =A0 =A0 =A0record_buf_mem[0] =3D 2;
> + =A0 =A0 =A0record_buf_mem[1] =3D u_regval + (immed_5 * 2);
> + =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D 1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> + =A0MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
> + =A0 =A0 =A0 =A0 =A0 =A0 record_buf_mem);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 101 insns. =A0*/
> +
> +static int
> +thumb_record_misc (insn_decode_record *thumb_insn_r)
> +{
> + =A0struct regcache *reg_cache =3D thumb_insn_r->regcache;
> +
> + =A0uint32_t opcode =3D 0, opcode1 =3D 0, opcode2 =3D 0;
> + =A0uint32_t register_bits =3D 0, register_count =3D 0;
> + =A0uint32_t register_list[8] =3D {0}, index =3D 0, start_address =3D 0;
> + =A0uint32_t record_buf[24], record_buf_mem[48];
> + =A0uint32_t reg_src1;
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0opcode =3D bits (thumb_insn_r->arm_insn, 11, 12);
> + =A0opcode1 =3D bits (thumb_insn_r->arm_insn, 8, 12);
> + =A0opcode2 =3D bits (thumb_insn_r->arm_insn, 9, 12);
> +
> + =A0if (14 =3D=3D opcode2)
> + =A0 =A0{
> + =A0 =A0 =A0/* POP. =A0*/
> + =A0 =A0 =A0register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0 =A0register_list[register_count++] =3D 1;
> + =A0 =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf[register_count] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0record_buf[register_count + 1] =3D ARM_SP_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D register_count + 2;
> + =A0 =A0 =A0for (register_count =3D 0; register_count < 8; register_coun=
t++)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if =A0(register_list[register_count])
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[index] =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0index++;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (10 =3D=3D opcode2)
> + =A0 =A0{
> + =A0 =A0 =A0/* PUSH. =A0*/
> + =A0 =A0 =A0register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_reg=
val);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0 =A0register_count++;
> + =A0 =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0start_address =3D u_regval - =A0\
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(4 * (bit (thumb_insn_r->arm_insn, 8=
) + register_count));
> + =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1] =3D start_a=
ddress;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf[0] =3D ARM_SP_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (0x1E =3D=3D opcode1)
> + =A0 =A0{
> + =A0 =A0 =A0/* BKPT insn. =A0*/
> + =A0 =A0 =A0/* Handle enhanced software breakpoint insn, BKPT. =A0*/
> + =A0 =A0 =A0/* CPSR is changed to be executed in ARM state, =A0disabling=
 normal
> + =A0 =A0 =A0 =A0 interrupts, entering abort mode. =A0*/
> + =A0 =A0 =A0/* According to high vector configuration PC is set. =A0*/
> + =A0 =A0 =A0/* User hits breakpoint and type reverse, in that case, we n=
eed
> to go back with
> + =A0 =A0 =A0previous CPSR and Program Counter. =A0*/
> + =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 2;
> + =A0 =A0 =A0/* We need to save SPSR value, which is not yet done. =A0*/
> + =A0 =A0 =A0printf_unfiltered (_("Process record does not support instru=
ction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0x%0x at address %=
s.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 thumb_insn_r->arm_i=
nsn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddress (thumb_ins=
n_r->gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 thumb_insn_r->this_=
addr));
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> + =A0else if ((0 =3D=3D opcode) || (1 =3D=3D opcode))
> + =A0 =A0{
> + =A0 =A0 =A0/* ADD(5), ADD(6). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0record_buf[0] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (2 =3D=3D opcode)
> + =A0 =A0{
> + =A0 =A0 =A0/* ADD(7), SUB(4). =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0record_buf[0] =3D ARM_SP_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> + =A0MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
> + =A0 =A0 =A0 =A0 =A0 =A0 record_buf_mem);
> +
> + =A0return 0;
> +}
> +
> +/* Handling opcode 110 insns. =A0*/
> +
> +static int
> +thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
> +{
> + =A0struct gdbarch_tdep *tdep =3D gdbarch_tdep (thumb_insn_r->gdbarch);
> + =A0struct regcache *reg_cache =3D thumb_insn_r->regcache;
> +
> + =A0uint32_t ret =3D 0; /* function return value: -1:record failure ;
> 0:success =A0*/
> + =A0uint32_t reg_src1 =3D 0;
> + =A0uint32_t opcode1 =3D 0, opcode2 =3D 0, register_bits =3D 0, register=
_count =3D 0;
> + =A0uint32_t register_list[8] =3D {0}, index =3D 0, start_address =3D 0;
> + =A0uint32_t record_buf[24], record_buf_mem[48];
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0opcode1 =3D bits (thumb_insn_r->arm_insn, 8, 12);
> + =A0opcode2 =3D bits (thumb_insn_r->arm_insn, 11, 12);
> +
> + =A0if (1 =3D=3D opcode2)
> + =A0 =A0{
> +
> + =A0 =A0 =A0/* LDMIA. =A0*/
> + =A0 =A0 =A0register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7);
> + =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0 =A0register_list[register_count++] =3D 1;
> + =A0 =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0record_buf[register_count] =3D reg_src1;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D register_count + 1;
> + =A0 =A0 =A0for (register_count =3D 0; register_count < 8; register_coun=
t++)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_list[register_count])
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0record_buf[index] =3D register_count;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0index++;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (0 =3D=3D opcode2)
> + =A0 =A0{
> + =A0 =A0 =A0/* It handles both STMIA. =A0*/
> + =A0 =A0 =A0register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7);
> + =A0 =A0 =A0/* Get Rn. =A0*/
> + =A0 =A0 =A0reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);
> + =A0 =A0 =A0regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval);
> + =A0 =A0 =A0while (register_bits)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0if (register_bits & 0x00000001)
> + =A0 =A0 =A0 =A0 =A0 =A0register_count++;
> + =A0 =A0 =A0 =A0 =A0register_bits =3D register_bits >> 1;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0start_address =3D u_regval;
> + =A0 =A0 =A0thumb_insn_r->mem_rec_count =3D register_count;
> + =A0 =A0 =A0while (register_count)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 1] =3D start_a=
ddress;
> + =A0 =A0 =A0 =A0 =A0record_buf_mem[(register_count * 2) - 2] =3D 4;
> + =A0 =A0 =A0 =A0 =A0start_address =3D start_address + 4;
> + =A0 =A0 =A0 =A0 =A0register_count--;
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (0x1F =3D=3D opcode1)
> + =A0 =A0{
> + =A0 =A0 =A0 =A0/* Handle arm syscall insn. =A0*/
> + =A0 =A0 =A0 =A0if (tdep->arm_swi_record !=3D NULL)
> + =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0ret =3D tdep->arm_swi_record(reg_cache);
> + =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("no syscall record support\=
n"));
> + =A0 =A0 =A0 =A0 =A0 =A0return -1;
> + =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0/* B (1), conditional branch is automatically taken care in process_=
record,
> + =A0 =A0as PC is saved there. =A0*/
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> + =A0MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,
> + =A0 =A0 =A0 =A0 =A0 =A0 record_buf_mem);
> +
> + =A0return ret;
> +}
> +
> +/* Handling opcode 111 insns. =A0*/
> +
> +static int
> +thumb_record_branch (insn_decode_record *thumb_insn_r)
> +{
> + =A0uint32_t record_buf[8];
> + =A0uint32_t bits_h =3D 0;
> +
> + =A0bits_h =3D bits (thumb_insn_r->arm_insn, 11, 12);
> +
> + =A0if (2 =3D=3D bits_h || 3 =3D=3D bits_h)
> + =A0 =A0{
> + =A0 =A0 =A0/* BL */
> + =A0 =A0 =A0record_buf[0] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 1;
> + =A0 =A0}
> + =A0else if (1 =3D=3D bits_h)
> + =A0 =A0{
> + =A0 =A0 =A0/* BLX(1). */
> + =A0 =A0 =A0record_buf[0] =3D ARM_PS_REGNUM;
> + =A0 =A0 =A0record_buf[1] =3D ARM_LR_REGNUM;
> + =A0 =A0 =A0thumb_insn_r->reg_rec_count =3D 2;
> + =A0 =A0}
> +
> + =A0/* B(2) is automatically taken care in process_record, as PC is
> + =A0 =A0 saved there. =A0*/
> +
> + =A0REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, reco=
rd_buf);
> +
> + =A0return 0;
> +}
> +
> +
> +/* Extracts arm/thumb/thumb2 insn depending on the size, and returns
> 0 on success
> +and positive val on fauilure. =A0*/
> +
> +static int
> +extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
> +{
> + =A0gdb_byte buf[insn_size];
> +
> + =A0memset (&buf[0], 0, insn_size);
> +
> + =A0if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
> + =A0 =A0return 1;
> + =A0insn_record->arm_insn =3D (uint32_t) extract_unsigned_integer (&buf[=
0],
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 insn_size,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 gdbarch_byte_order =
(insn_record->gdbarch));
> + =A0return 0;
> +}
> +
> +typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
> +
> +/* Decode arm/thumb insn depending on condition cods and opcodes; and
> + =A0 dispatch it. =A0*/
> +
> +static int
> +decode_insn (insn_decode_record *arm_record, record_type_t record_type,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0uint32_t insn_size)
> +{
> +
> + =A0/* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
> instruction. =A0*/
> + =A0static const sti_arm_hdl_fp_t const arm_handle_insn[8] =3D
> + =A0{
> + =A0 =A0arm_record_data_proc_misc_ld_str, =A0 /* 000. =A0*/
> + =A0 =A0arm_record_data_proc_imm, =A0 =A0 =A0 =A0 =A0 /* 001. =A0*/
> + =A0 =A0arm_record_ld_st_imm_offset, =A0 =A0 =A0 =A0/* 010. =A0*/
> + =A0 =A0arm_record_ld_st_reg_offset, =A0 =A0 =A0 =A0/* 011. =A0*/
> + =A0 =A0arm_record_ld_st_multiple, =A0 =A0 =A0 =A0 =A0/* 100. =A0*/
> + =A0 =A0arm_record_b_bl, =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* 101. =
=A0*/
> + =A0 =A0arm_record_coproc, =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* 110. =
=A0*/
> + =A0 =A0arm_record_coproc_data_proc =A0 =A0 =A0 =A0 /* 111. =A0*/
> + =A0};
> +
> + =A0/* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
> instruction. =A0*/
> + =A0static const sti_arm_hdl_fp_t const thumb_handle_insn[8] =3D
> + =A0{ \
> + =A0 =A0thumb_record_shift_add_sub, =A0 =A0 =A0 =A0/* 000. =A0*/
> + =A0 =A0thumb_record_add_sub_cmp_mov, =A0 =A0 =A0/* 001. =A0*/
> + =A0 =A0thumb_record_ld_st_reg_offset, =A0 =A0 /* 010. =A0*/
> + =A0 =A0thumb_record_ld_st_imm_offset, =A0 =A0 /* 011. =A0*/
> + =A0 =A0thumb_record_ld_st_stack, =A0 =A0 =A0 =A0 =A0/* 100. =A0*/
> + =A0 =A0thumb_record_misc, =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* 101. =A0*/
> + =A0 =A0thumb_record_ldm_stm_swi, =A0 =A0 =A0 =A0 =A0/* 110. =A0*/
> + =A0 =A0thumb_record_branch =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* 111. =A0*/
> + =A0};
> +
> + =A0uint32_t ret =3D 0; =A0 =A0/* return value: negative>failure =A0 0>s=
uccess. =A0*/
> + =A0uint32_t insn_id =3D 0;
> +
> + =A0if (extract_arm_insn (arm_record, insn_size))
> + =A0 =A0{
> + =A0 =A0 =A0if (record_debug)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record: error reading =
memory at "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"addr %s len=
 =3D %d.\n"),
> + =A0 =A0 =A0 =A0 =A0paddress (arm_record->gdbarch, arm_record->this_addr=
),
> insn_size);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> + =A0else if (ARM_RECORD =3D=3D record_type)
> + =A0 =A0{
> + =A0 =A0 =A0arm_record->cond =3D bits (arm_record->arm_insn, 28, 31);
> + =A0 =A0 =A0insn_id =3D bits (arm_record->arm_insn, 25, 27);
> + =A0 =A0 =A0ret =3D arm_record_extension_space (arm_record);
> + =A0 =A0 =A0/* If this insn has fallen into extension space
> + =A0 =A0 =A0 =A0 then we need not decode it anymore. =A0*/
> + =A0 =A0 =A0if (ret !=3D -1 && !INSN_RECORDED(arm_record))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0ret =3D arm_handle_insn[insn_id] (arm_record);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> + =A0else if (THUMB_RECORD =3D=3D record_type)
> + =A0 =A0{
> + =A0 =A0 =A0/* As thumb does not have condition codes, we set negative. =
=A0*/
> + =A0 =A0 =A0arm_record->cond =3D -1;
> + =A0 =A0 =A0insn_id =3D bits (arm_record->arm_insn, 13, 15);
> + =A0 =A0 =A0ret =3D thumb_handle_insn[insn_id] (arm_record);
> + =A0 =A0}
> + =A0else if (THUMB2_RECORD =3D=3D record_type)
> + =A0 =A0{
> + =A0 =A0 =A0printf_unfiltered (_("Process record doesnt support thumb32 =
instruction "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0x%0x at address %=
s.\n"),arm_record->arm_insn,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddress (arm_recor=
d->gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 arm_record->this_ad=
dr));
> + =A0 =A0 =A0ret =3D -1;
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0/* Throw assertion. =A0*/
> + =A0 =A0 =A0gdb_assert (0);
> + =A0 =A0}
> +
> + =A0return ret;
> +}
> +
> +
> +/* Cleans up local record registers and memory allocations. =A0*/
> +
> +static void
> +deallocate_reg_mem (insn_decode_record *record)
> +{
> + =A0xfree (record->arm_regs);
> + =A0xfree (record->arm_mems);
> +}
> +
> +
> +/* Parse the current instruction and record the values of the registers =
and
> + =A0 memory that will be changed in current instruction to record_arch_l=
ist".
> + =A0 Return -1 if something is wrong. =A0*/
> +
> +int
> +arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0CORE_ADDR insn_addr)
> +{
> +
> + =A0enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch);
> + =A0uint32_t no_of_rec =3D 0;
> + =A0uint32_t ret =3D 0; =A0/* return value: -1:record failure ; =A00:suc=
cess =A0*/
> + =A0ULONGEST t_bit =3D 0, insn_id =3D 0;
> +
> + =A0ULONGEST u_regval =3D 0;
> +
> + =A0insn_decode_record arm_record;
> +
> + =A0memset (&arm_record, 0, sizeof (insn_decode_record));
> + =A0arm_record.regcache =3D regcache;
> + =A0arm_record.this_addr =3D insn_addr;
> + =A0arm_record.gdbarch =3D gdbarch;
> +
> +
> + =A0if (record_debug > 1)
> + =A0 =A0{
> + =A0 =A0 =A0fprintf_unfiltered (gdb_stdlog, "Process record: arm_process=
_record "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0"addr =3D %s\n",
> + =A0 =A0 =A0paddress (gdbarch, arm_record.this_addr));
> + =A0 =A0}
> +
> + =A0if (extract_arm_insn (&arm_record, 2))
> + =A0 =A0{
> + =A0 =A0 =A0if (record_debug)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0printf_unfiltered (_("Process record: error reading =
memory at "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "addr %s len =
=3D %d.\n"),
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddress (arm_r=
ecord.gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 arm_record.this=
_addr), 2);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0return -1;
> + =A0 =A0}
> +
> + =A0/* Check the insn, whether it is thumb or arm one. =A0*/
> +
> + =A0t_bit =3D arm_psr_thumb_bit (arm_record.gdbarch);
> + =A0regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_r=
egval);
> +
> +
> + =A0if (!(u_regval & t_bit))
> + =A0 =A0{
> + =A0 =A0 =A0/* We are decoding arm insn. =A0*/
> + =A0 =A0 =A0ret =3D decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_=
BYTES);
> + =A0 =A0}
> + =A0else
> + =A0 =A0{
> + =A0 =A0 =A0insn_id =3D bits (arm_record.arm_insn, 11, 15);
> + =A0 =A0 =A0/* is it thumb2 insn? =A0*/
> + =A0 =A0 =A0if ((0x1D =3D=3D insn_id) || (0x1E =3D=3D insn_id) || (0x1F =
=3D=3D insn_id))
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0ret =3D decode_insn (&arm_record, THUMB2_RECORD,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 THUMB2_INSN_SIZ=
E_BYTES);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0else
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0/* We are decoding thumb insn. =A0*/
> + =A0 =A0 =A0 =A0 =A0ret =3D decode_insn (&arm_record, THUMB_RECORD, THUM=
B_INSN_SIZE_BYTES);
> + =A0 =A0 =A0 =A0}
> + =A0 =A0}
> +
> + =A0if (0 =3D=3D ret)
> + =A0 =A0{
> + =A0 =A0 =A0/* Record registers. =A0*/
> + =A0 =A0 =A0record_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM=
);
> + =A0 =A0 =A0if (arm_record.arm_regs)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0for (no_of_rec =3D 0; no_of_rec < arm_record.reg_rec=
_count;
> no_of_rec++)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if (record_arch_list_add_reg (arm_record.reg=
cache ,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0arm_record.arm_regs[no_of_rec]))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D -1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0/* Record memories. =A0*/
> + =A0 =A0 =A0if (arm_record.arm_mems)
> + =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0for (no_of_rec =3D 0; no_of_rec < arm_record.mem_rec=
_count;
> no_of_rec++)
> + =A0 =A0 =A0 =A0 =A0 =A0{
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if (record_arch_list_add_mem
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((CORE_ADDR)arm_record.arm_mems[no_o=
f_rec].addr,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0arm_record.arm_mems[no_of_rec].len))
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D -1;
> + =A0 =A0 =A0 =A0 =A0 =A0}
> + =A0 =A0 =A0 =A0}
> +
> + =A0 =A0 =A0if (record_arch_list_add_end ())
> + =A0 =A0 =A0 =A0ret =3D -1;
> + =A0 =A0}
> +
> +
> + =A0deallocate_reg_mem (&arm_record);
> +
> + =A0return ret;
> +}
> +
> +
> diff -urN arm_orig/arm-tdep.h arm_new/arm-tdep.h
> --- arm_orig/arm-tdep.h 2011-12-03 18:06:39.000000000 +0530
> +++ arm_new/arm-tdep.h =A02011-12-03 17:52:28.000000000 +0530
> @@ -201,6 +201,9 @@
> =A0 /* Return the expected next PC if FRAME is stopped at a syscall
> =A0 =A0 =A0instruction. =A0*/
> =A0 CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
> +
> + =A0 /* Parse swi insn args, sycall record. =A0*/
> + =A0int (*arm_swi_record) (struct regcache *regcache);
> =A0};
>
> =A0/* Structures used for displaced stepping. =A0*/
> @@ -330,6 +333,8 @@
> =A0 =A0instruction? =A0*/
> =A0extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
>
> +extern int arm_process_record (struct gdbarch *gdbarch,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct regc=
ache *regcache, CORE_ADDR addr);
> =A0/* Functions exported from armbsd-tdep.h. =A0*/
>
> =A0/* Return the appropriate register set for the core section identified