From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) by sourceware.org (Postfix) with ESMTPS id B7077384A00F for ; Sat, 18 Apr 2020 11:18:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B7077384A00F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nelson.chu@sifive.com Received: by mail-il1-x132.google.com with SMTP id f2so4847481ilq.7 for ; Sat, 18 Apr 2020 04:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PvEE8QnSZ2p+T1NmzOHF9BTom0ZAkcv4mi5tvKvvdug=; b=NcHQ4qnnbBQhUQK/iVRbP8UY/MWkAKLnkQDyChTHR2al+4j1wh8xfZHbC3tv/ataP8 qRAGxPtyJPIxrFGfQ7d6zGY+Sc8tqivY3EeqoT+n6sq+E5gCcjZNWEPJhc46m5D4po/L PFaZq9DqrGpl+wpJAaJZYReB2aAqriEEr6Apb4RsR10rvqOPGcnPa/Ke8iBBPCRJ8NCz AVUYcK5kvN5c3cKiPmy75iELQ919wWqnYlc2HmR//4xOfuHpYmUUFKJLTwX5SloX10k+ /+uCE5rrFG80s+THbzC/IJjyJm8y2YThQcO8U0lUfE7rQuHaE+FC/SwPY74kN31d6x+M GEgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PvEE8QnSZ2p+T1NmzOHF9BTom0ZAkcv4mi5tvKvvdug=; b=exlJVVIpTZrBzafTRoNeIvd3/i2v797G+F950AAIqgd+51odds+K77qQFbDDHW156o bjEpHYxcds9D5p5JKIiREki8lp1ENgJusZHp/LMslIs+eybMH3J/1xvJXeliUtI7V+IK H27pXzlTsyXWHmwPoxmYivXch6YHYp/uYKPKWrdo0bQnguRwX6/SgNKvZm2GgQEqjPrF XoxYJ23wF9XVzeu/XJiOjW3oeVPsXzzbaSDb6ZRUD9XatMb6wcDzHAc4lcImM/M2kkSA qcLvLN4XaOVmIoANa+IQEWtI7UeWYZMsjifGuTKKZVC2jxXlEt+54nhmekF0C0rIz8Pj 9ORg== X-Gm-Message-State: AGi0PuZgppBhjNsBtVx/t1YYeTbeVkJ866BcN1aP0mI78rHvz6Fk98Iz dDHBOjGJgnYSuDB7qxRAtjNF2kruYJf58kCbT5Y18g== X-Google-Smtp-Source: APiQypLa4YG11SzFagxZao0UmiNIUds4efWIJ0vHVTqwNKX7l2EF2hkMAYLsictuWYAWhRG/9Lez8P97Dbc6JnUhrbo= X-Received: by 2002:a92:3b11:: with SMTP id i17mr7620098ila.161.1587208735954; Sat, 18 Apr 2020 04:18:55 -0700 (PDT) MIME-Version: 1.0 References: <1587208075-2462-1-git-send-email-nelson.chu@sifive.com> <1587208075-2462-6-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1587208075-2462-6-git-send-email-nelson.chu@sifive.com> From: Nelson Chu Date: Sat, 18 Apr 2020 19:18:47 +0800 Message-ID: Subject: Re: [PATCH 5/7] RISC-V: Make privilege spec attributes work. To: Binutils , gdb-patches@sourceware.org Cc: Andrew Burgess , Andrew Waterman , asb@lowrisc.org, Kito Cheng , Maxim Blinov , Jim Wilson , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-24.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Apr 2020 11:19:00 -0000 CC Palmer. Thanks Nelson On Sat, Apr 18, 2020 at 7:08 PM Nelson Chu wrote: > > There are three privilege spec attributes, Tag_RISCV_priv_spec, > Tag_RISCV_priv_spec_minor and Tag_RISCV_priv_spec_revision, are used to choose > which version of privilege spec you want. You can also use -mpriv-spec option > to choose the priv spec, but the priority of ELF attributes is the highest. > > Beside, we have to make sure all arch and priv attributes are set before any > instruction. > > The Priority of these options, > * ELF priv attributes > -mpriv-spec > --with-priv-spec > > bfd/ > * elfxx-riscv.c (riscv_parsing_subset_version): Remove the static. > (riscv_estimate_digit): Likewise. > * elfxx-riscv.h: Updated. > > gas/ > * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to > explicit_attr. Set it to TRUE if any ELF attribute is found. > (riscv_set_default_priv_version): Try to set the default_priv_spec if > the priv attributes are set, and their value are meaningful (!= 0p0p0). > (md_assemble): Set the default_priv_version according to the priv > attributes when we start to assemble instruction. > > (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to > riscv_write_out_attrs. Update the arch and priv attributes. If we > don't set the corresponding ELF attributes, then try to output the > default ones. > (riscv_set_public_attributes): If any ELF attribute or -march-attr > options is set (explicit_attr is TRUE), then call riscv_write_out_attrs > to update the arch and priv attributes. > (s_riscv_attribute): Make sure all arch and priv attributes are set > before any instruction. > > * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any > ELF attribute or -march-attr is set. If the priv attributes are not > set, then try to update them by the default setting (-mpriv-spec or > --with-priv-spec). > * testsuite/gas/riscv/attribute-02.d: Likewise. > * testsuite/gas/riscv/attribute-03.d: Likewise. > * testsuite/gas/riscv/attribute-04.d: Likewise. > * testsuite/gas/riscv/attribute-06.d: Likewise. > * testsuite/gas/riscv/attribute-07.d: Likewise. > * testsuite/gas/riscv/attribute-08.d: Likewise. > * testsuite/gas/riscv/attribute-09.d: Likewise. > * testsuite/gas/riscv/attribute-10.d: Likewise. > * testsuite/gas/riscv/attribute-11.d: Likewise. > * testsuite/gas/riscv/attribute-unknown.d: Likewise. > > * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated > priv attributes according to the -mpriv-spec option. > * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. > * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. > * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. > > * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv version > set by priv attributes must be supported. > * testsuite/gas/riscv/attribute-05.s: Likewise. > > ld/ > * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. > * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. > * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. > * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. > --- > bfd/elfxx-riscv.c | 4 +- > bfd/elfxx-riscv.h | 12 ++ > gas/config/tc-riscv.c | 165 ++++++++++++++++++--- > gas/testsuite/gas/riscv/attribute-01.d | 3 + > gas/testsuite/gas/riscv/attribute-02.d | 3 + > gas/testsuite/gas/riscv/attribute-03.d | 3 + > gas/testsuite/gas/riscv/attribute-04.d | 3 + > gas/testsuite/gas/riscv/attribute-05.d | 4 +- > gas/testsuite/gas/riscv/attribute-05.s | 4 +- > gas/testsuite/gas/riscv/attribute-06.d | 3 + > gas/testsuite/gas/riscv/attribute-07.d | 3 + > gas/testsuite/gas/riscv/attribute-08.d | 3 + > gas/testsuite/gas/riscv/attribute-09.d | 3 + > gas/testsuite/gas/riscv/attribute-10.d | 3 + > gas/testsuite/gas/riscv/attribute-11.d | 3 + > gas/testsuite/gas/riscv/attribute-unknown.d | 3 + > .../gas/riscv/priv-reg-fail-version-1p10.d | 10 +- > .../gas/riscv/priv-reg-fail-version-1p11.d | 10 +- > .../gas/riscv/priv-reg-fail-version-1p9.d | 10 +- > .../gas/riscv/priv-reg-fail-version-1p9p1.d | 11 +- > ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 + > ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 + > ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 + > ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s | 4 +- > ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s | 4 +- > ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d | 4 +- > ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 3 + > .../ld-riscv-elf/attr-merge-strict-align-01.d | 3 + > .../ld-riscv-elf/attr-merge-strict-align-02.d | 3 + > .../ld-riscv-elf/attr-merge-strict-align-03.d | 3 + > .../ld-riscv-elf/attr-merge-strict-align-04.d | 3 + > .../ld-riscv-elf/attr-merge-strict-align-05.d | 3 + > 32 files changed, 266 insertions(+), 36 deletions(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 3a6aaf3..3ac66f1 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1028,7 +1028,7 @@ riscv_elf_add_sub_reloc (bfd *abfd, > `std_ext_p`: True if parsing std extension. > `use_default_version`: Set it to True if we need the default version. */ > > -static const char * > +const char * > riscv_parsing_subset_version (riscv_parse_subset_t *rps, > const char *march, > const char *p, > @@ -1771,7 +1771,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list) > > /* Return the number of digits for the input. */ > > -static size_t > +size_t > riscv_estimate_digit (unsigned num) > { > size_t digit = 0; > diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h > index e3d5177..145ea2e 100644 > --- a/bfd/elfxx-riscv.h > +++ b/bfd/elfxx-riscv.h > @@ -87,6 +87,15 @@ riscv_parse_subset (riscv_parse_subset_t *, > bfd_boolean); > > extern const char * > +riscv_parsing_subset_version (riscv_parse_subset_t *, > + const char *, > + const char *, > + unsigned *, > + unsigned *, > + bfd_boolean, > + bfd_boolean *); > + > +extern const char * > riscv_supported_std_ext (void); > > extern void > @@ -95,6 +104,9 @@ riscv_release_subset_list (riscv_subset_list_t *); > extern char * > riscv_arch_str (unsigned, const riscv_subset_list_t *); > > +extern size_t > +riscv_estimate_digit (unsigned); > + > /* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z, > "xargs" corresponds to RV_ISA_CLASS_X, etc. Order is important > here. */ > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 6528a03..9ce9046 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -283,8 +283,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; > /* Indicate we are already assemble any instructions or not. */ > static bfd_boolean start_assemble = FALSE; > > -/* Indicate arch attribute is explictly set. */ > -static bfd_boolean explicit_arch_attr = FALSE; > +/* Indicate ELF attributes are explictly set. */ > +static bfd_boolean explicit_attr = FALSE; > > /* Macros for encoding relaxation state for RVC branches and far jumps. */ > #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ > @@ -614,15 +614,67 @@ static int > riscv_set_default_priv_version (const char *s) > { > enum riscv_csr_vclass class; > - if (!riscv_get_priv_version_class (s, &class)) > + unsigned major, minor, revision; > + obj_attribute *attr; > + size_t buf_size; > + char *buf; > + > + /* Find the corresponding version class. */ > + if (riscv_get_priv_version_class (s, &class)) > + { > + default_priv_spec = class; > + return 1; > + } > + > + if (s != NULL) > { > as_bad (_("Unsupported RISC-V privilege version set by " > "-mpriv-spec=%s."), s); > return 0; > } > + > + /* Try to set the default_priv_spec according to the priv attributes. */ > + attr = elf_known_obj_attributes_proc (stdoutput); > + major = (unsigned) attr[Tag_RISCV_priv_spec].i; > + minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i; > + revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i; > + > + /* The priv attributes setting 0p0p0 is meaningless. We should have set > + the default_priv_spec by md_parse_option and riscv_after_parse_args, so > + just skip the following setting. */ > + if (major == 0 && minor == 0 && revision == 0) > + return 1; > + > + buf_size = riscv_estimate_digit (major) > + + 1 /* 'p' */ > + + riscv_estimate_digit (minor) > + + 1; /* string terminator */ > + > + if (revision != 0) > + { > + buf_size += 1 /* 'p' */ > + + riscv_estimate_digit (revision); > + buf = xmalloc (buf_size); > + snprintf (buf, buf_size, "%dp%dp%d", major, minor, revision); > + } > else > - default_priv_spec = class; > - return 1; > + { > + buf = xmalloc (buf_size); > + snprintf (buf, buf_size, "%dp%d", major, minor); > + } > + > + if (riscv_get_priv_version_class (buf, &class)) > + { > + default_priv_spec = class; > + free (buf); > + return 1; > + } > + > + /* Still can not find the version class. */ > + as_bad (_("Unsupported RISC-V privilege version set by " > + "priv attributes `%dp%dp%d'."), major, minor, revision); > + free (buf); > + return 0; > } > > /* Init hash table csr_extra_hash to handle CSR. */ > @@ -2511,9 +2563,17 @@ md_assemble (char *str) > expressionS imm_expr; > bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; > > - const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); > + /* The arch and priv attributes should be set before assembling. */ > + if (!start_assemble) > + { > + start_assemble = TRUE; > > - start_assemble = TRUE; > + /* Set the default_priv_version according to the priv attributes. */ > + if (!riscv_set_default_priv_version (NULL)) > + return; > + } > + > + const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); > > if (error) > { > @@ -3526,26 +3586,78 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) > demand_empty_rest_of_line (); > } > > -/* Update arch attributes. */ > +/* Update arch and priv attributes. If we don't set the corresponding ELF > + attributes, then try to output the default ones. */ > > static void > -riscv_write_out_arch_attr (void) > +riscv_write_out_attrs (void) > { > - const char *arch_str = riscv_arch_str (xlen, &riscv_subsets); > + riscv_parse_subset_t rps; > + const char *arch_str, *priv_str, *end; > + char *priv_str_t, *p; > + unsigned int p_count; > + unsigned major, minor, revision, empty; > > + /* Re-write arch attribute to normalize the arch string. */ > + arch_str = riscv_arch_str (xlen, &riscv_subsets); > bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str); > - > xfree ((void *)arch_str); > + > + /* For the file without any instruction, we don't set the default_priv_version > + according to the priv attributes since the md_assemble isn't called. > + Call riscv_set_default_priv_version here for the above case, although > + it seems strange. */ > + if (!start_assemble > + && !riscv_set_default_priv_version (NULL)) > + return; > + > + /* Re-write priv attributes by default_priv_spec. */ > + priv_str = riscv_get_priv_version_name (default_priv_spec); > + priv_str_t = xstrdup (priv_str); > + > + /* Split the version string into two parts, the first part is major + minor, > + and the second part is the revision if possible. */ > + for (p = priv_str_t, p_count = 0; *p != '\0'; p++) > + { > + if (*p == 'p') > + p_count++; > + if (p_count == 2) > + { > + *p++ = '\0'; > + break; > + } > + } > + > + /* Borrow riscv_parsing_subset_version to parse the priv version string. */ > + rps.subset_list = NULL; > + rps.error_handler = as_fatal; > + rps.xlen = &xlen; > + rps.get_default_version = NULL; > + > + /* Parse the version string twice. */ > + end = riscv_parsing_subset_version (&rps, priv_str, priv_str_t, > + &major, &minor, TRUE, NULL); > + end = riscv_parsing_subset_version (&rps, priv_str, p, > + &revision, &empty, TRUE, NULL); > + if (*end != '\0') > + as_fatal (_("Failed to parse the priv version: %s"), priv_str); > + > + /* Insert the priv attributes. */ > + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, major); > + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, minor); > + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, revision); > + xfree ((void *)priv_str_t); > } > > -/* Add the default contents for the .riscv.attributes section. */ > +/* Add the default contents for the .riscv.attributes section. If any > + ELF attribute or -march-attr options is set, call riscv_write_out_attrs > + to update the arch and priv attributes. */ > > static void > riscv_set_public_attributes (void) > { > - if (riscv_opts.arch_attr || explicit_arch_attr) > - /* Re-write arch attribute to normalize the arch string. */ > - riscv_write_out_arch_attr (); > + if (riscv_opts.arch_attr || explicit_attr) > + riscv_write_out_attrs (); > } > > /* Called after all assembly has been done. */ > @@ -3599,13 +3711,14 @@ static void > s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) > { > int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); > + unsigned old_xlen; > + obj_attribute *attr; > > - if (tag == Tag_RISCV_arch) > + explicit_attr = TRUE; > + switch (tag) > { > - unsigned old_xlen = xlen; > - > - explicit_arch_attr = TRUE; > - obj_attribute *attr; > + case Tag_RISCV_arch: > + old_xlen = xlen; > attr = elf_known_obj_attributes_proc (stdoutput); > if (!start_assemble) > riscv_set_arch (attr[Tag_RISCV_arch].s, FALSE); > @@ -3624,6 +3737,18 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) > > /* We also need to update the version of ISA here. */ > riscv_set_arch (default_riscv_isa_version, TRUE); > + break; > + > + case Tag_RISCV_priv_spec: > + case Tag_RISCV_priv_spec_minor: > + case Tag_RISCV_priv_spec_revision: > + /* We will not set the priv versions until md_assemble. */ > + if (start_assemble) > + as_fatal (_(".attribute priv spec must set before any instructions")); > + break; > + > + default: > + break; > } > } > > diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d > index 3f9e841..dedd443 100644 > --- a/gas/testsuite/gas/riscv/attribute-01.d > +++ b/gas/testsuite/gas/riscv/attribute-01.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d > index a58248e..5368741 100644 > --- a/gas/testsuite/gas/riscv/attribute-02.d > +++ b/gas/testsuite/gas/riscv/attribute-02.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d > index 04b9ab5..6d7c781 100644 > --- a/gas/testsuite/gas/riscv/attribute-03.d > +++ b/gas/testsuite/gas/riscv/attribute-03.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d > index 8a3f51b..b725e2d 100644 > --- a/gas/testsuite/gas/riscv/attribute-04.d > +++ b/gas/testsuite/gas/riscv/attribute-04.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d > index 3309ff3..16c19e9 100644 > --- a/gas/testsuite/gas/riscv/attribute-05.d > +++ b/gas/testsuite/gas/riscv/attribute-05.d > @@ -7,5 +7,5 @@ File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" > Tag_RISCV_unaligned_access: Unaligned access > Tag_RISCV_priv_spec: 1 > - Tag_RISCV_priv_spec_minor: 2 > - Tag_RISCV_priv_spec_revision: 3 > + Tag_RISCV_priv_spec_minor: 9 > + Tag_RISCV_priv_spec_revision: 1 > diff --git a/gas/testsuite/gas/riscv/attribute-05.s b/gas/testsuite/gas/riscv/attribute-05.s > index 3b3b7f6..4920309 100644 > --- a/gas/testsuite/gas/riscv/attribute-05.s > +++ b/gas/testsuite/gas/riscv/attribute-05.s > @@ -1,6 +1,6 @@ > .attribute arch, "rv32g" > .attribute priv_spec, 1 > - .attribute priv_spec_minor, 2 > - .attribute priv_spec_revision, 3 > + .attribute priv_spec_minor, 9 > + .attribute priv_spec_revision, 1 > .attribute unaligned_access, 1 > .attribute stack_align, 16 > diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d > index 5c8a5c6..b963b6e 100644 > --- a/gas/testsuite/gas/riscv/attribute-06.d > +++ b/gas/testsuite/gas/riscv/attribute-06.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d > index 20ac9be..f383f94 100644 > --- a/gas/testsuite/gas/riscv/attribute-07.d > +++ b/gas/testsuite/gas/riscv/attribute-07.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv64i2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d > index 7f580d3..1391b56 100644 > --- a/gas/testsuite/gas/riscv/attribute-08.d > +++ b/gas/testsuite/gas/riscv/attribute-08.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32e1p9" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d > index 77c7ef3..14f1b85 100644 > --- a/gas/testsuite/gas/riscv/attribute-09.d > +++ b/gas/testsuite/gas/riscv/attribute-09.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i1p9_f2p0_v0p9_zicsr0p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d > index 9c72035..7518197 100644 > --- a/gas/testsuite/gas/riscv/attribute-10.d > +++ b/gas/testsuite/gas/riscv/attribute-10.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p1_zicsr2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-11.d b/gas/testsuite/gas/riscv/attribute-11.d > index bc7f986..c4e8b0a 100644 > --- a/gas/testsuite/gas/riscv/attribute-11.d > +++ b/gas/testsuite/gas/riscv/attribute-11.d > @@ -4,3 +4,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p1_zicsr2p1" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d > index 667f21a..120e3de 100644 > --- a/gas/testsuite/gas/riscv/attribute-unknown.d > +++ b/gas/testsuite/gas/riscv/attribute-unknown.d > @@ -4,5 +4,8 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > Tag_unknown_255: "test" > Tag_unknown_256: 123 \(0x7b\) > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d > index d7a788a..ff7c5f8 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d > @@ -1,3 +1,11 @@ > -#as: -march=rv32if -mcsr-check -mpriv-spec=1p10 > +#as: -march=rv32if -mcsr-check -mpriv-spec=1p10 -march-attr > #source: priv-reg.s > #warning_output: priv-reg-fail-version-1p10.l > +#readelf: -A > + > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: 1 > + Tag_RISCV_priv_spec_minor: 10 > +#... > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d > index 2830c83..7e79c02 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d > @@ -1,3 +1,11 @@ > -#as: -march=rv32if -mcsr-check -mpriv-spec=1p11 > +#as: -march=rv32if -mcsr-check -mpriv-spec=1p11 -march-attr > #source: priv-reg.s > #warning_output: priv-reg-fail-version-1p11.l > +#readelf: -A > + > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: 1 > + Tag_RISCV_priv_spec_minor: 11 > +#... > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d > index 70c405f..372505f 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d > @@ -1,3 +1,11 @@ > -#as: -march=rv32if -mcsr-check -mpriv-spec=1p9 > +#as: -march=rv32if -mcsr-check -mpriv-spec=1p9 -march-attr > #source: priv-reg.s > #warning_output: priv-reg-fail-version-1p9.l > +#readelf: -A > + > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: 1 > + Tag_RISCV_priv_spec_minor: 9 > +#... > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d > index 2bd4bbf..dc204b0 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d > @@ -1,3 +1,12 @@ > -#as: -march=rv32if -mcsr-check -mpriv-spec=1p9p1 > +#as: -march=rv32if -mcsr-check -mpriv-spec=1p9p1 -march-attr > #source: priv-reg.s > #warning_output: priv-reg-fail-version-1p9p1.l > +#readelf: -A > + > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: 1 > + Tag_RISCV_priv_spec_minor: 9 > + Tag_RISCV_priv_spec_revision: 1 > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > index 5baaba4..032f964 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > @@ -7,3 +7,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > index a7d79a1..54a7621 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > @@ -7,3 +7,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > index d46dee8..67f0437 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > @@ -7,3 +7,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s > index 1ad9500..0b7ffea 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s > @@ -1,3 +1,3 @@ > .attribute priv_spec, 1 > - .attribute priv_spec_minor, 2 > - .attribute priv_spec_revision, 3 > + .attribute priv_spec_minor, 9 > + .attribute priv_spec_revision, 1 > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s > index 1ad9500..0b7ffea 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s > @@ -1,3 +1,3 @@ > .attribute priv_spec, 1 > - .attribute priv_spec_minor, 2 > - .attribute priv_spec_revision, 3 > + .attribute priv_spec_minor, 9 > + .attribute priv_spec_revision, 1 > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d > index dc4c4e0..0aa6fe0 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d > @@ -8,5 +8,5 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > Tag_RISCV_priv_spec: 1 > - Tag_RISCV_priv_spec_minor: 2 > - Tag_RISCV_priv_spec_revision: 3 > + Tag_RISCV_priv_spec_minor: 9 > + Tag_RISCV_priv_spec_revision: 1 > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d > index 7a5bc81..5585fac 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d > @@ -8,3 +8,6 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_stack_align: 16-bytes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d > index 1039930..91011a2 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d > @@ -8,3 +8,6 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > Tag_RISCV_unaligned_access: Unaligned access > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d > index 12ca1c4..5bdea27 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d > @@ -8,3 +8,6 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > Tag_RISCV_unaligned_access: Unaligned access > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d > index e41351d..ac886fb 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d > @@ -8,3 +8,6 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > Tag_RISCV_unaligned_access: Unaligned access > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d > index ac2a766..dd45f76 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d > @@ -7,3 +7,6 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d > index 608c05e..ef0c154 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d > @@ -8,3 +8,6 @@ Attribute Section: riscv > File Attributes > Tag_RISCV_arch: [a-zA-Z0-9_\"].* > Tag_RISCV_unaligned_access: Unaligned access > + Tag_RISCV_priv_spec: [0-9_\"].* > + Tag_RISCV_priv_spec_minor: [0-9_\"].* > +#... > -- > 2.7.4 >