From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-il1-x141.google.com (mail-il1-x141.google.com [IPv6:2607:f8b0:4864:20::141]) by sourceware.org (Postfix) with ESMTPS id BB044393BC33 for ; Tue, 19 May 2020 09:08:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org BB044393BC33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nelson.chu@sifive.com Received: by mail-il1-x141.google.com with SMTP id 4so12733979ilg.1 for ; Tue, 19 May 2020 02:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Ur/laoItm2tC/1+/k3YyiX3GgZn3eMjuF/HX8rq2j/s=; b=F297WTnw2MUo1ncey0EjrFJ5/rZt9hOyUAOEnNaLV0HsQFOF5le8Z6af8rfqU8l/CB saaK/XuMVU/MKG+3ZtGK6THoYfmpOWX7Y8G7+6gzV3yHM4g/i7GoNw926dUz6eor+dwZ Rr137EZQqSmlwSyrDiJf0ULO87JAA7kP1gf4pew8WohrTwUpMNlF9Bvmx0OADIEvhvy/ hxkuRJO7w9Wg9DEMRehYHwyIcXOzLrHskJajlaN/quytP/5MAisana1SDAVpVOGt6p24 2yyrZaGJlsoCsaQqSelQ2RpmDkn3aWDhq5T3Ws77YfBiFh7ULmBomg9p17JadxrBGGIb GDpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Ur/laoItm2tC/1+/k3YyiX3GgZn3eMjuF/HX8rq2j/s=; b=FwNXr4bCgb66x3auOAw51GG/TKO0GJdHw9iaIVULa8PasdHG2AeDigkBl/OusgqfJT F6SlbJoyuMH52TLnXekxnZOPt6fLNC6dVKvLnK3sa3iO9EzS7XwsQO4536+dF+fJC4T8 aB9e2BvIoe0YmxtunKBYXpHbyHdlRA04e1DgK9es9j+gEJjdnrFu+JHJLsF61PADCGR4 f4+8cs7BnfpxrunAmaYy39XhlLL8wzf+vYovXDRadqM72Iq7CIE1TQ9VqYvhfoUOdUuZ /Uu3ODzMpzvYND/26rdSFqn9XUSJU43qQVvk6fx8YtSA+fd66nvcgE0aP+S1U3MFRuXS uFWw== X-Gm-Message-State: AOAM532pbgdqs5w8RdLcA8yfx6qtaKAoyyMlh8HQivOqHqDW4bLU/uVg hUeZNgba6u5hkr+fsoTStvQp4vsK32Jgd2mlUT/70g== X-Google-Smtp-Source: ABdhPJw3EUV6iI4TimyJHSvBe0Zbgz9IWj2iJrzRergWcx6rjiTZzXhrtgsnb9cyBmYzelM1VIPz6giRreU76bZ6hFo= X-Received: by 2002:a92:6411:: with SMTP id y17mr17082620ilb.161.1589879324058; Tue, 19 May 2020 02:08:44 -0700 (PDT) MIME-Version: 1.0 References: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com> <1588733747-18787-10-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1588733747-18787-10-git-send-email-nelson.chu@sifive.com> From: Nelson Chu Date: Tue, 19 May 2020 17:08:32 +0800 Message-ID: Subject: Re: [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options. To: Binutils , gdb-patches@sourceware.org Cc: Palmer Dabbelt , Kito Cheng , Jim Wilson , Andrew Waterman , Andrew Burgess , Alex Bradbury , Maxim Blinov Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 May 2020 09:08:46 -0000 PING :) On Wed, May 6, 2020 at 10:56 AM Nelson Chu wrote: > > gas/ > * config/tc-riscv.c (md_show_usage): Add descriptions about > the new GAS options. > * doc/c-riscv.texi: Likewise. > > opcodes/ > * riscv-dis.c (print_riscv_disassembler_options): Add description > about the new OBJDUMP option. > --- > gas/config/tc-riscv.c | 18 ++++++++++-------- > gas/doc/c-riscv.texi | 16 ++++++++++++++++ > opcodes/riscv-dis.c | 10 +++++++--- > 3 files changed, 33 insertions(+), 11 deletions(-) > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 6e30a06..b08339c 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -3469,14 +3469,16 @@ md_show_usage (FILE *stream) > { > fprintf (stream, _("\ > RISC-V options:\n\ > - -fpic generate position-independent code\n\ > - -fno-pic don't generate position-independent code (default)\n\ > - -march=3DISA set the RISC-V architecture\n\ > - -mabi=3DABI set the RISC-V ABI\n\ > - -mrelax enable relax (default)\n\ > - -mno-relax disable relax\n\ > - -march-attr generate RISC-V arch attribute\n\ > - -mno-arch-attr don't generate RISC-V arch attribute\n\ > + -fpic generate position-independent code\n\ > + -fno-pic don't generate position-independent code (= default)\n\ > + -march=3DISA set the RISC-V architecture\n\ > + -misa-spec=3DISAspec set the RISC-V ISA spec (2.2, 20190608, = 20191213)\n\ > + -mpriv-spec=3DPRIVspec set the RISC-V privilege spec (1.9, 1.9.= 1, 1.10, 1.11)\n\ > + -mabi=3DABI set the RISC-V ABI\n\ > + -mrelax enable relax (default)\n\ > + -mno-relax disable relax\n\ > + -march-attr generate RISC-V arch attribute\n\ > + -mno-arch-attr don't generate RISC-V arch attribute\n\ > ")); > } > > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi > index 488cf56..bf942c3 100644 > --- a/gas/doc/c-riscv.texi > +++ b/gas/doc/c-riscv.texi > @@ -42,6 +42,22 @@ Don't generate position-independent code (default) > @cindex @samp{-march=3DISA} option, RISC-V > @item -march=3DISA > Select the base isa, as specified by ISA. For example -march=3Drv32ima. > +If this option and the architecture attributes aren=E2=80=99t set, then = assembler > +will check the default configure setting --with-arch=3DISA. > + > +@cindex @samp{-misa-spec=3DISAspec} option, RISC-V > +@item -misa-spec=3DISAspec > +Select the default isa spec version. If the version of ISA isn't set > +by -march, then assembler helps to set the version according to > +the default chosen spec. If this option isn't set, then assembler will > +check the default configure setting --with-isa-spec=3DISAspec. > + > +@cindex @samp{-mpriv-spec=3DPRIVspec} option, RISC-V > +@item -mpriv-spec=3DPRIVspec > +Select the privileged spec version. We can decide whether the CSR is va= lid or > +not according to the chosen spec. If this option and the privilege attr= ibutes > +aren't set, then assembler will check the default configure setting > +--with-priv-spec=3DPRIVspec. > > @cindex @samp{-mabi=3DABI} option, RISC-V > @item -mabi=3DABI > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index c5a0d36..f1f20c6 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -603,11 +603,15 @@ The following RISC-V-specific disassembler options = are supported for use\n\ > with the -M switch (multiple options should be separated by commas):\n")= ); > > fprintf (stream, _("\n\ > - numeric Print numeric register names, rather than ABI names.\n")= ); > + numeric Print numeric register names, rather than ABI names.\n= ")); > > fprintf (stream, _("\n\ > - no-aliases Disassemble only into canonical instructions, rather\n\ > - than into pseudoinstructions.\n")); > + no-aliases Disassemble only into canonical instructions, rather\n= \ > + than into pseudoinstructions.\n")); > + > + fprintf (stream, _("\n\ > + priv-spec=3DPRIV Print the CSR according to the chosen privilege spec= \n\ > + (1.9, 1.9.1, 1.10, 1.11).\n")); > > fprintf (stream, _("\n")); > } > -- > 2.7.4 >