From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 114276 invoked by alias); 22 Jan 2020 02:16:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 114149 invoked by uid 89); 22 Jan 2020 02:15:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy=claim X-HELO: mail.kernel.org Received: from mail.kernel.org (HELO mail.kernel.org) (198.145.29.99) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 02:15:52 +0000 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F146724672 for ; Wed, 22 Jan 2020 02:15:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579659351; bh=EovyKOCEuSF0bgBD4NMMn+5nXJ9aFN4UmAwL4czF8oE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=o8h5WXA9Xhe6kF5nagUUpRyg58gIA+JygYuTntSEPDeykCCJUaNzzwHcmhv9mrM3W YtU7KQQpuErO29QuXjfQTona/2q9+TUTug05WFuWZ5j2j9QjWIToUfWFiRd1Hu2PwK eQMTEw4DZQfhB5G0oGeJ5cN/zZcE3XeeAY7NvNcY= Received: by mail-lf1-f46.google.com with SMTP id b15so4049310lfc.4 for ; Tue, 21 Jan 2020 18:15:50 -0800 (PST) MIME-Version: 1.0 References: <00e401d5cb52$63a4d000$2aee7000$@c-sky.com> In-Reply-To: From: Guo Ren Date: Wed, 22 Jan 2020 05:26:00 -0000 Message-ID: Subject: Re: [PATCH] riscv: add gdbserver support To: Jim Wilson Cc: jiangshuai_li@c-sky.com, Maciej Rozycki , Andrew Burgess , gdb-patches@sourceware.org, =?UTF-8?B?5aSP56uL5pa5?= , yunhai_shang Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2020-01/txt/msg00666.txt.bz2 Hi Jim, On Tue, Jan 21, 2020 at 7:04 AM Jim Wilson wrote: > > > 3. vector regitsers r/w > > The vector registers are still in draft form, and are subject to > change. I'd rather not add support for draft features upstream, as > then we are stuck supporting draft versions of the ISA forever. Also, > we still don't have a proposal for DWARF register numbers for the > vector registers. In fact, both T-HEAD XuanTie C910 and Andes 27-series CPU cores claim to support vector extensions, which is good for riscv-v extenstion. Many complex linux vector development/test-suite need linux/gdb/glibc to support the vector-regs' context. So I think these basic functions for linux/gdb/glibc should be merged in advance, rather than waiting for the entire vector spec to freeze. After all, register save / restore is only a small part of riscv-v and very basic, maybe the part of registers(abi) could be frozen in the vector spec in advance. Here is the linux riscv-v port V2 for task_switch, singal, ptrace: [1] [1]: https://lore.kernel.org/linux-riscv/20200116143029.31441-4-guoren@kernel.org/ Best Regrads Guo Ren