From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 58367 invoked by alias); 19 Nov 2018 03:51:38 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 58352 invoked by uid 89); 19 Nov 2018 03:51:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=H*f:sk:2018110, fflags, fpu, documents X-HELO: mail-vs1-f68.google.com Received: from mail-vs1-f68.google.com (HELO mail-vs1-f68.google.com) (209.85.217.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Nov 2018 03:51:36 +0000 Received: by mail-vs1-f68.google.com with SMTP id b74so16941936vsd.9 for ; Sun, 18 Nov 2018 19:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=G6r52qIr+UcvppMIuP4nixBu/gal6taoCASaFSwXOfg=; b=Hw2+UHoZtajHTHImb8oGVZpeFjAbws4RlM3QS4o/9INcDrzb2lL57NPCXy43CLD5Ia kElT3TdBPapDG3gZiMoEC+x3DGHC0OFmBr1TI0WExP4ZZ6rkftp+bp93UhWngw8kY2RL qEIJAtET4UkQ2WyFGq0z5ZM8VOJLJ9//gfpm+t5o7zjam09TjFsMappOU9dZ0OTfYXiX 5yJs+lVn33Dm6F+jKiWVygFVbgNvZlHgfa++CP0s8ulK0lkNFkDDrJr4UwlfgGkWb5eD y44uq5S1Q8QtZYJXnWw9nvdIW10uJSt55amBCvhg0oIY/s8783TfX3/+y8y7HbQh/yP4 1ncg== MIME-Version: 1.0 References: <20181108160745.24600-1-andrew.burgess@embecosm.com> <20181114145756.GM16539@embecosm.com> In-Reply-To: <20181114145756.GM16539@embecosm.com> From: Jim Wilson Date: Mon, 19 Nov 2018 03:51:00 -0000 Message-ID: Subject: Re: [PATCH] gdb/riscv: Add target description support To: Andrew Burgess Cc: gdb-patches@sourceware.org, Palmer Dabbelt , John Baldwin Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-11/txt/msg00284.txt.bz2 On Wed, Nov 14, 2018 at 6:58 AM Andrew Burgess wrote: > I'm proposing to merge this version if everyone is happy with it. Looks like a few minor typos in the new docs, but otherwise it looks good to me. I tested this riscv-linux native on a HiFive Unleashed board, and with riscv-tests/debug using openocd and spike. > +The @samp{org.gnu.gdb.riscv.fpu} feature is optional. If present it > +should contains registers @samp{f0} through @samp{f31}, @samp{fflags}, > +@samp{frm}, and @samp{fcsr}. As with the cpu feature either the > +architectural register names, or the ABI names can be used. "should contains registers" -> "should contain registers" > +The @samp{org.gnu.gdb.riscv.virtual} feature is optional. If present > +it should contain registers that are not backed by real registers on > +the target but are instead virtual, where the register value is > +derived from other target state. In many ways these are like GDBs > +pseudo-registers, except implemented by the target. Currently the > +only register expected in this set is the one byte @samp{priv} > +register that contains the targets privilege level in the least > +significant two bits. "targets privilege level" -> "target's privilege level" > +The @samp{org.gnu.gdb.riscv.csr} feature is optional. If present it > +should contain all of the targets standard CSRs. Standard CSRs are > +those defined in the RISC-V specification documents. There is some > +overlap between this feature and the fpu feature; the @samp{fflags}, > +@samp{frm}, and @samp{fcsr} registers could be in either feature. The > +expectation is that these registers will be in the fpu feature if the > +target has floating point hardware, but can be moved into the csr > +feature if the target has the floating point control registers, but no > +other floating point hardware. "targets standard CSRs" -> "target's standard CSRs" Jim