From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 44973 invoked by alias); 23 Jul 2018 15:38:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 44962 invoked by uid 89); 23 Jul 2018 15:38:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=H*RU:209.85.221.65, HX-HELO:sk:mail-wr, tries, Hx-spam-relays-external:209.85.221.65 X-HELO: mail-wr1-f65.google.com Received: from mail-wr1-f65.google.com (HELO mail-wr1-f65.google.com) (209.85.221.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Jul 2018 15:38:17 +0000 Received: by mail-wr1-f65.google.com with SMTP id c13-v6so1184756wrt.1 for ; Mon, 23 Jul 2018 08:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=hIIXKvdOtWP+Xbp66IMjoQQn6c8mgbpmYNlu1IgTq6o=; b=MT9lGeVP/zyqycbBIvwHUEBTdiQv+7xXwAXgcqFF3boVqSgUB5oURZ9VjXwON/qrCD nDUd6QOBaO+qAm/r3X1kRtAwf6UjMGBOuIR6kKqgnP7fR+ri68hhgIWtJb1bUtb4Nbzq 7Xj9CDg9Nzax0QrHZADXI7kR454ukHhNVbri5wjh0xCqRNxfa8Td7nRdYBRxAPNPezZF a5y6yyoZVAkWWnoSvvEjBZHootrS+E8zkNgfHCXjDZ34/zDESs/D2oy+WiUqXWWfCFbP 8riQ6j5nxojw4FgxD8eMymdBlD6rR+QAB+vU7U8JRkcp7gslo4g645sZ5bXdhpYMgv+S Nx0A== MIME-Version: 1.0 Received: by 2002:adf:e44b:0:0:0:0:0 with HTTP; Mon, 23 Jul 2018 08:38:14 -0700 (PDT) In-Reply-To: <71103f9b-f83b-7e68-1d56-f30038473936@embedded-brains.de> References: <20180717001241.25908-1-jimw@sifive.com> <71103f9b-f83b-7e68-1d56-f30038473936@embedded-brains.de> From: Jim Wilson Date: Mon, 23 Jul 2018 15:38:00 -0000 Message-ID: Subject: Re: [PATCH] RISC-V: Don't decrement pc after break. To: Sebastian Huber Cc: gdb-patches@sourceware.org, Andrew Burgess Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-07/txt/msg00665.txt.bz2 On Mon, Jul 23, 2018 at 3:30 AM, Sebastian Huber wrote: > Hello Jim, > > this patch broke debugging with Qemu (qemu-system-riscv64, Git commit > 6598f0cdad6acc6674c4f060fa46e537228c2c47). The GDB error message is: > > Register 3921 is not available I don't understand how rtems debugging could have worked without this patch. 3921 minus 65 in hex is 0xf10 which is the legacy misa. The legacy misa is checked only if a read of the v1.9.1 misa fails. If the read of both the v1.9.1 misa and the legacy misa fails, then you get a confusing error stating that register 3921 is not available. But the real problem is that both misa reads failed. The ISA spec says that misa must exist and be readable, although an implementation is allowed to return 0 when it is read. Gdb uses misa to determine target features. Gdb does handle the 0 read case by deducing info from ELF header flags instead of the misa register. If you have a rtems target support, then it must handle reading the misa register. If is OK to just return 0. That is what my linux port does for now. At some point I may try adding a linux kernel patch to add ptrace support for reading misa. If rtems is running in machine mode, you can probably read misa directly. Otherwise, you would need something like a linux ptrace to read it. For embedded targets using openocd, they can just read misa directly. The problem with misa is easy to miss, as gdb only tries to read misa if you execute a command that requires info about the target, such as trying to use hardware floating point. Actually, one of my other patches, the one to remove the pc decrement after a break, modified the code so that we try to read misa when checking to see if compressed breakpoints could be used. Before it was only checking ELF headers for this, which wasn't right. This is probably the patch that exposed the bug in your rtems target support. Jim