From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 44067 invoked by alias); 9 Aug 2018 17:25:33 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 44052 invoked by uid 89); 9 Aug 2018 17:25:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=metal X-HELO: mail-wm0-f67.google.com Received: from mail-wm0-f67.google.com (HELO mail-wm0-f67.google.com) (74.125.82.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 09 Aug 2018 17:25:31 +0000 Received: by mail-wm0-f67.google.com with SMTP id y2-v6so983433wma.1 for ; Thu, 09 Aug 2018 10:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=KW7CP/okk7RlAthv0pT323IYKVj0Tk2PEEYxLY8o2/o=; b=l6ThXIn4rxtlo4b9AlOcd1lEHCx11wGrK1xRr4dKY547gOvr1Z5ir4vsYm6SyHW3T+ EtcjD2+ovhDkYf7pj7y16PqT893e/l0lePhz8RnRKPSUPBK+MN2UT7U8nzxIN5tXzAxw /T++83Jti6LN9C649okZbEDgA0nhPb4TiPcHEnlPVYo2KSygHDkUT3nOVzFKlK4pao6X nBWDOZ5V1e99uUo30qHpWiFuy+Q0vujaKcdyJUg5M6MmXlXrMxcqCPlH/7HOyS2BXnTL H5py1dFEdn0qN37bkjfD5qFSq9sFvK5bfVVFZxIHY9Gw15zmfj+4jUbouZveXPFEr8Lf OeMA== MIME-Version: 1.0 Received: by 2002:adf:e44b:0:0:0:0:0 with HTTP; Thu, 9 Aug 2018 10:25:28 -0700 (PDT) In-Reply-To: <831sb7pumd.fsf@gnu.org> References: <878t5gjv94.fsf@tromey.com> <83600kp8pc.fsf@gnu.org> <831sb7pumd.fsf@gnu.org> From: Jim Wilson Date: Thu, 09 Aug 2018 17:25:00 -0000 Message-ID: Subject: Re: [PATCH 5/5] RISC-V: Add configure support riscv*-linux*. To: Eli Zaretskii Cc: Tom Tromey , Palmer Dabbelt , gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-08/txt/msg00222.txt.bz2 On Thu, Aug 9, 2018 at 5:55 AM, Eli Zaretskii wrote: > Thanks. So you are saying that building on a 64-bit hosts will enable > this by default, while a 32-bit build with --enable-64-bit-bfd only > makes sense if --enable-targets=all is also used, is that right? I didn't actually test that, but trying it, yes, this is how it works. If I'm on a 32-bit host, and use --enable-targets=all, I only get 32-bit targets enabled. If I'm on a 32-bit host and use --enable-targets=all --enable-64-bit-bfd then I get both 32-bit and 64-bit targets enabled. This requires that the C/C++ compiler supports long long. FYI for my riscv build experiment, with an unpatched gdb i.e. only the riscv bare metal support, a 32-bit hosted --enable-targets=all gdb does build and run. There is no bfd elf riscv support, only the bfd cpu-riscv.o file was built. The gdb riscv-tdep.o file was built and linked in. But without the bfd support I can't trigger it, so it appears to be harmless dead code. If I load a riscv32-elf binary, info target just says elf32-little, and disassembling code gives me ARM v7 instructions, which must be the default if it can't recognize an object file. I think that there can only be a problem if a gdb target port is making direct calls into the bfd target elf support, in which case that target port would have to be in the 64-bit object file list. The riscv linux port is not doing that currently, and I'm not sure if it ever would need to. But I can try another build after I get my riscv linux patches all checked in. Jim