Re: [PATCH] riscv: add gdbserver support

Guo Ren
2020-01-22T02:16:08Z

Hi Jim,

On Tue, Jan 21, 2020 at 7:04 AM Jim Wilson <jimw@sifive.com> wrote:
>
> > 3. vector regitsers r/w
>
> The vector registers are still in draft form, and are subject to
> change. I'd rather not add support for draft features upstream, as
> then we are stuck supporting draft versions of the ISA forever. Also,
> we still don't have a proposal for DWARF register numbers for the
> vector registers.
In fact, both T-HEAD XuanTie C910 and Andes 27-series CPU cores claim
to support vector extensions, which is good for riscv-v extenstion.
Many complex linux vector development/test-suite need linux/gdb/glibc
to support the vector-regs' context.
So I think these basic functions for linux/gdb/glibc should be merged
in advance, rather than waiting for the entire vector spec to freeze.
After all, register save / restore is only a small part of riscv-v and
very basic, maybe the part of registers(abi) could be frozen in the
vector spec in advance.

Here is the linux riscv-v port V2 for task_switch, singal, ptrace: [1]

[1]: https://lore.kernel.org/linux-riscv/20200116143029.31441-4-guoren@kernel.org/

Best Regrads
Guo Ren