From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 100251 invoked by alias); 20 Jan 2020 23:04:23 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 100239 invoked by uid 89); 20 Jan 2020 23:04:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=him X-HELO: mail-vs1-f68.google.com Received: from mail-vs1-f68.google.com (HELO mail-vs1-f68.google.com) (209.85.217.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 20 Jan 2020 23:04:21 +0000 Received: by mail-vs1-f68.google.com with SMTP id b79so578305vsd.9 for ; Mon, 20 Jan 2020 15:04:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3bGmYgq9wzCu+dC+YLHpjM3Hs6ZsTWFS/Zy1aOKD5r0=; b=D04/+m7wpKkFb+4M1NdnZ3zF8xrmmEBE0G9bxWAnhV+uV0Vlf+fscdZL7D6HNilB7f lT3TSJk+p6DYWr4OsMeLnrke0I1QHS3NQo6fYA9P9FaFYCQ9urWCHIr56nYhVrVZGjD5 phpl26xGUQpFe1tfZREMlNoH4wW5a8xciwK2TYR2oakwuKGHWxh2WLn1hSXmJy0abdv8 UoAcDLzkyipZubS/aeApZ7AzcV5YWDM1VJngIcaX7oHv2/EfgU78MHwO0if86TzwXrMe vm82MWkyOP907gM6bCJ78YQIEs5FodHxDUUTW6sj8U1YgsMnTwfvahscA7Xve05kAND0 ds6Q== MIME-Version: 1.0 References: <00e401d5cb52$63a4d000$2aee7000$@c-sky.com> In-Reply-To: <00e401d5cb52$63a4d000$2aee7000$@c-sky.com> From: Jim Wilson Date: Mon, 20 Jan 2020 23:33:00 -0000 Message-ID: Subject: Re: [PATCH] riscv: add gdbserver support To: jiangshuai_li@c-sky.com, Maciej Rozycki Cc: Andrew Burgess , guoren@kernel.org, gdb-patches@sourceware.org, =?UTF-8?B?5aSP56uL5pa5?= , yunhai_shang Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-01/txt/msg00615.txt.bz2 On Tue, Jan 14, 2020 at 7:18 PM wrote: > This patch is a base support for Riscv32 and Riscv64 arch. It implemented > how to > r/w gprs and fprs, identify the software bkpt insns and the *.dat files for > regs_info. > I have tested it on kernel 5.1.15, and it works normally. I believe that Maciej has a RISC-V gdbserver port also. It would be nice to see some comment from him. > Some requirements may be implemented later: > 1. if fpu has 64bits in riscv32 This is common, and will have to be fixed, but not necessarily fixed in the first version. We also have riscv32 linux targets with no FP registers. I don't know what the *.dat files are for, but I think the general registers and the FP registers should be separate files if possible. If not, then we need 6 dat files, as we have 2 general reg sizes and 3 FP reg sizes, and 2*3=6. > 2. hardware bkpt/watchpoint support As far as I know, the linux kernel can't set hardware breakpoints with the current design of the RISC-V debug standard. They can only be set via jtag. So I don't see this as a problem. > 3. vector regitsers r/w The vector registers are still in draft form, and are subject to change. I'd rather not add support for draft features upstream, as then we are stuck supporting draft versions of the ISA forever. Also, we still don't have a proposal for DWARF register numbers for the vector registers. Jim