From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 124729 invoked by alias); 8 Aug 2018 17:55:44 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 124720 invoked by uid 89); 8 Aug 2018 17:55:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f67.google.com Received: from mail-wm0-f67.google.com (HELO mail-wm0-f67.google.com) (74.125.82.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 08 Aug 2018 17:55:42 +0000 Received: by mail-wm0-f67.google.com with SMTP id o11-v6so3600231wmh.2 for ; Wed, 08 Aug 2018 10:55:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=VVfGMmoeSSLSWw5ZVPij841DBSKvpWVm8MfNpfWiJ8Y=; b=BtF6C8+RdYv3PIW8HGDTzQ+kwGhzQ7R56SUYzuvVET3eYWSz4cabJRXh0R0sq1Uhq9 BrEFy85NkdFXhryLPxIdToyjlQ2CPJ1GV5BifCzjBBoOsjTRYWoktNSWoa4uZOJku19Q MpO/RUyNyTuumAT6jbTM3MwErM3l7XIyKJYm/4cZVgZXKq2v1d/Bw2IwMturm++ynSwz ivP09sH8WHepnVqYJZsPQvF85Qe5nlRLKTN8lNpfA0afAmnvxkpxAgQLD/vJGJbsE1xw jFZPrLEujwP19Ps5UvGLm70VPa07n8AiLmY8d+CM94IBMzX4u16hqX7T+6Lv3X+6/M4H JyEQ== MIME-Version: 1.0 Received: by 2002:adf:e44b:0:0:0:0:0 with HTTP; Wed, 8 Aug 2018 10:55:40 -0700 (PDT) In-Reply-To: <20180808125052.GM3155@embecosm.com> References: <20180808021607.7652-1-jimw@sifive.com> <20180808125052.GM3155@embecosm.com> From: Jim Wilson Date: Wed, 08 Aug 2018 17:55:00 -0000 Message-ID: Subject: Re: [PATCH 2/5] RISC-V: Add software single step support. To: Andrew Burgess Cc: gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-08/txt/msg00173.txt.bz2 On Wed, Aug 8, 2018 at 5:50 AM, Andrew Burgess wrote: > * Jim Wilson [2018-08-07 19:16:07 -0700]: >> gdb/ >> * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes. >> (decode_register_index_short): New. >> (decode_j_type_insn, decode_cj_type_insn): New. >> (decode_b_type_insn, decode_cb_type_insn): New. >> (riscv_insn::decode): Add support for jumps, branches, lr, and sc. New >> local xlen. Check xlen when decoding ambiguous compressed insns. In >> compressed decode, use is_c_lui_insn instead of is_lui_insn, and >> is_c_sw_insn instead of is_sw_insn. >> (riscv_next_pc, riscv_next_pc_atomic_sequence): New. >> (riscv_software_single_step): New. >> * riscv-tdep.h (riscv_software_single_step): Declare. > > Looks good to me. Committed. Jim