From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71412 invoked by alias); 23 Jul 2018 23:27:31 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 71394 invoked by uid 89); 23 Jul 2018 23:27:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=vacation X-HELO: mail-wm0-f65.google.com Received: from mail-wm0-f65.google.com (HELO mail-wm0-f65.google.com) (74.125.82.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Jul 2018 23:27:29 +0000 Received: by mail-wm0-f65.google.com with SMTP id s9-v6so679871wmh.3 for ; Mon, 23 Jul 2018 16:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=rTw94tw0MnyOjuBih/zj8twO84C4XwaLnk5vmmav7lY=; b=H6ZZCL8r6DLRVV6YHBJnUQl9sqi+KR4AOHJzYFEjQ3DxO7g0voXbuFUqZz5DGjzey2 VEWUXv00sZSKacI4/1JxVwO1YQWu++SUtRi7ry74qUwUPFmKBZ+Ib5PoLWsmvZaVPd9W aHr2omYrLrXBB7lYTTP8Nq9eEoFthe/tctmoHLNkyXIif2vLQJV6rTQVD+ElNXra/7xT 4IAIlLizCmT/TuSe7hnqwNOf+AJPrh3SCpCQ0N+siWjIg8Nd4DHYmn1KtbkO6VyXDFnR tSvcBWjE1ky0p2u4JMvJWdofCf5E1C4zfapU+uohzCY8o16KryAPtZAyV/u0e8khIKd5 uSCg== MIME-Version: 1.0 Received: by 2002:adf:e44b:0:0:0:0:0 with HTTP; Mon, 23 Jul 2018 16:27:26 -0700 (PDT) In-Reply-To: <1830811266.24706.1532366683342.JavaMail.zimbra@embedded-brains.de> References: <20180717001241.25908-1-jimw@sifive.com> <71103f9b-f83b-7e68-1d56-f30038473936@embedded-brains.de> <1830811266.24706.1532366683342.JavaMail.zimbra@embedded-brains.de> From: Jim Wilson Date: Mon, 23 Jul 2018 23:27:00 -0000 Message-ID: Subject: Re: [PATCH] RISC-V: Don't decrement pc after break. To: Sebastian Huber Cc: gdb-patches@sourceware.org, Andrew Burgess Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2018-07/txt/msg00672.txt.bz2 On Mon, Jul 23, 2018 at 10:24 AM, Sebastian Huber wrote: >> The problem with misa is easy to miss, as gdb only tries to read misa >> if you execute a command that requires info about the target, such as >> trying to use hardware floating point. Actually, one of my other >> patches, the one to remove the pc decrement after a break, modified >> the code so that we try to read misa when checking to see if >> compressed breakpoints could be used. Before it was only checking ELF >> headers for this, which wasn't right. This is probably the patch that >> exposed the bug in your rtems target support. > > This could be also a Qemu bug. I have to check this with the debugger tom= orrow. The misa should be returned by Qemu in csr_read_helper() (target/ris= cv/op_helper.c). A "info registers" for example returns only the standard r= egisters. For the CSR registers I get "not available". Sorry, I see that you did point at the right patch. I'm on vacation, and not able to give this my full attention at the moment. What should happen here is that gdb calls fetch_registers, which then uses some target specific way to access registers. In the linux native support, there is a function defined that uses ptrace to read registers. I don't know what happens in the openocd case. If you are using target remote, then you are using the fetch_registers call in remote.c, which means the problem is in the target gdbstub. Looking at old qemu in riscv-gnu-toolchain, I see in target-riscv/gdbstub.c in riscv_cpu_gdb_read_register that it only handles the first 65 registers, which are the int, pc, and fp registers. Looking at new qemu in freedom-u-sdk, I see in target/riscv/gdbstub.c that the riscv_cpu_gdb_read_register function is handling the csrs, and looks OK. So maybe the problem is that the qemu you are using is too old? Jim