From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 121717 invoked by alias); 21 Sep 2018 17:26:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 121700 invoked by uid 89); 21 Sep 2018 17:26:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f65.google.com Received: from mail-ot1-f65.google.com (HELO mail-ot1-f65.google.com) (209.85.210.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 21 Sep 2018 17:26:00 +0000 Received: by mail-ot1-f65.google.com with SMTP id n5-v6so13745032otl.5 for ; Fri, 21 Sep 2018 10:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=eni27R+E+nU8hhBXVihXl7vwItIfHlucEV8ATDI3ZVo=; b=kGgFVPUieujtwTYsE4t1+P1me68s5EtLAcoR0eIVhoBFWUGpC6RX4whhWi2BAxJCuy /QbZ0R99YuP6hxewhssBKDezE28yD4HQuNLRRr/RmzrtObStEXe+FjpHuPanZKsz6A9s VoPN/aCsiCo5EKNIrKrnPZrnifHdGANF5gH3W/G0jnySoLniZopwEDwY/P/pvBL8D+9d IVfDo8yaSx2WFF4N6Yb5d+F0x6o3Y8pWNUPi+Y1HhJ8x4rEuTY52KgjqZc/qobq6SOa1 rppcmP5qEnFWU5mMcFKRQw1tMgJpCvgsKSlPqtbaekyWKfs7QDxfyhEt2qktX6ouMe5m 1mZg== MIME-Version: 1.0 References: <20180919231950.22634-1-jhb@FreeBSD.org> <20180919231950.22634-3-jhb@FreeBSD.org> <0081bdf8-04cb-f6b7-d80a-d9a878d0a3ab@FreeBSD.org> <20180920215146.GW5952@embecosm.com> <4e2b6d40-dc15-6caa-8520-90289ce972da@FreeBSD.org> <20180921092721.GY5952@embecosm.com> In-Reply-To: <20180921092721.GY5952@embecosm.com> From: Jim Wilson Date: Fri, 21 Sep 2018 17:26:00 -0000 Message-ID: Subject: Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register. To: Andrew Burgess Cc: John Baldwin , gdb-patches@sourceware.org, Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-09/txt/msg00754.txt.bz2 On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess wrote: > Jim: Given that we agree that targets should definitely provide a > value for misa, at a minimum just returning the constant 0. But, > given that GDB already defaults to 0 in some cases anyway. And the > spec is quite clear that 0 is the right default value in the absence > of anything better, would you be OK with a patch that does return a > default of 0? The patch to decode an instruction to decide whether to use a compressed breakpoint or not solves my main problem. There is also the issue of finding FP register size, but since we only support rv64gc at the moment, it isn't a serious problem. Also, I think the linker kernel may already be passing FP info via auxvec/hwcap, so I think we already have an alternate solution for that which just needs to be implemented. I haven't looked at that yet. So yes, I think it is OK to start defaulting misa to 0. FYI I have a qemu patch, which I may someday finish, that adds XML register support to the RISC-V qemu system-mode port, which allows qemu to provide a correct value of misa. We know that misa accesses already work with embedded targets via OpenOCD. So it is just linux and freebsd that need to worry about misa. The qemu patch is here, though it looks like github is confused by rebasing and the patch isn't readable anymore. https://github.com/riscv/riscv-qemu/pull/160 I'll have to figure out how to fix that. Jim