Re: [RFA/commit] arm-tdep.c: Do not single-step after hitting a watchpoint

Peter Maydell
2014-09-30T10:01:16Z

On 30 September 2014 10:08, Pedro Alves <palves@redhat.com> wrote:
> On 09/29/2014 11:53 PM, Peter Maydell wrote:
>> There's an assertion in this LKML post from 2010:
>> https://lkml.org/lkml/2010/4/14/127
>> that v7 cores do actually all generate synchronous
>> watchpoint exceptions (even though architecturally
>> they're permitted not to). Was your test h/w a v6?
>
> Joel's test was against qemu (without your patch).
>
> Terry's tests were against armv7l and armv8. Both synchronous.
>
> The report that confuses me is Gareth's:
>
> https://sourceware.org/ml/gdb/2014-09/msg00013.html
>
> As it sounds like he has v7-m hardware that has asynchronous
> behavior. Gareth, can you confirm this, please?

In general it's unwise to assume that statements
about the ARM A and R profiles carry across to M
profile... v7M profile watchpoints are rather
different from v7AR watchpoints in terms of how you
set them, how they're reported, etc, and they're
always asynchronous (other insns may execute after
the one which triggers the wp before the debug event
fires).

> Still, in any case, from that LKML post:
>
> "v6 cores are the opposite; they only generate asynchronous
> watchpoint exceptions".
>
> So, eh!? Does your qemu patch take this into account? Seems
> like it should.

My QEMU patch is for the built in gdbstub, which is
completely different code to the emulation of the
CPU's own architected debug hardware. (We implement
the latter only for v7 and above, not v6.)

It doesn't seem very sensible to me to deliberately
provide unhelpful asynchronous watchpoint support
on v6-and-lower guest CPUs just because that's what
the hardware does, especially since it would mean we
wouldn't interoperate with current gdb. (Similarly,
we provide watchpoint support in our stub even if
the CPU we're emulating has no watchpoint support
of its own at all. Think of us as like a JTAG probe.)

> Now I'm confused on the mention of the Linux kernel
> subtracting 8 from the PC to help GDB. I can't find that
> anywhere in the kernel's sources.

This is a reference to the standard ARM exception
entry behaviour where the value saved to the link
register may be +2, +4 or +8 from the "preferred
return address" for the exception. The kernel handles
this via a 'vector_stub' macro that adjusts the
value read from LR so the rest of the kernel can
deal simply in preferred return addresses. Since
sync. watchpoints are a kind of data abort they
go through here, with a correction value of 8:
http://lxr.free-electrons.com/source/arch/arm/kernel/entry-armv.S#L1043

thanks
-- PMM