From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 66021 invoked by alias); 14 Aug 2018 18:14:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 66005 invoked by uid 89); 14 Aug 2018 18:14:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=funny, psp, PSP, Dec X-HELO: mail-oi0-f41.google.com Received: from mail-oi0-f41.google.com (HELO mail-oi0-f41.google.com) (209.85.218.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 14 Aug 2018 18:14:55 +0000 Received: by mail-oi0-f41.google.com with SMTP id j205-v6so35354404oib.4 for ; Tue, 14 Aug 2018 11:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=G7S6/Uuk+LM5zoR4gkYp1CNQOhNi0MQKp2G69s8yMJk=; b=bpBakM+jlN0n1d9xUwsKxZ89ot6Wp6oEu4JONdY/mG9sX9VLL6aIpibt//xwV1Ujmb zR5BU1D8FLi/aW7U3/CI2hoZ8+WdIqZWW3ferdHs1OdsHWD2hkBDNAZdB6MTSoABgxcs 0CQcV0Yx5KVO2QkbpG54gY4bWJb69GzeI1yhUPHhJXJAhck1piax1UYHJ2s+nuTp6ZHr CwKLxY3XA8h/Db3t2DdzpKpAoBzXQocNZyDxkrq24+woDqva4MbqCb3wZYokSB5NOucr vQJEnVbzyLgvhn8Wu6QnjHo9hFkuPNOLl4zGE2CFiRdvveYtHnAejoQ5Kf3LG7b7EM1e Ujew== MIME-Version: 1.0 References: <566F108D.1000401@redhat.com> <566F5B1A.8040703@redhat.com> In-Reply-To: From: Christopher Friedt Date: Tue, 14 Aug 2018 18:14:00 -0000 Message-ID: Subject: Re: cortex-m xml register descriptions for m-system To: Tristan Gingold Cc: Pedro Alves , Yao Qi , gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-08/txt/msg00356.txt.bz2 I might be going for the Guiness record of the longest delay in a thread! Kind of funny, but I was using gdb / QEMU again, and found that I was missing some critical registers again. In any case, let's continue the conversation. On Thu., Dec. 17, 2015, 3:31 a.m. Tristan Gingold, wrote: > I think that only PSP and SP are required (of course SP could be MSP). > I think I agree that only the psp and sp are required (not the msp). That would mean the following should be added for armv7-m: psp, primask, basepri, faultmask, control and the following would need to be added for armv6-m: psp, faultmask, control However, we also have the armv8-m and the following would need to be added for armv8-m: psp, msplim, psplim, primask, basepri, basepri_max, faultmask, control, msp_ns, psp_ns, msplim_ns, psplim_ns, primask_ns, basepri_ns, faultmask_ns, control_ns, sp_ns. Does all of that make sense? I think I could probably throw together a patch and just put it on the list, if that's ok. >