From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 119077 invoked by alias); 5 Jan 2016 06:45:07 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 119045 invoked by uid 89); 5 Jan 2016 06:45:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=D*atmel.com, maps, column, unwind X-HELO: eusmtp01.atmel.com Received: from eusmtp01.atmel.com (HELO eusmtp01.atmel.com) (212.144.249.243) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 05 Jan 2016 06:45:04 +0000 Received: from apsmtp01.atmel.com (10.168.254.30) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Tue, 5 Jan 2016 07:44:56 +0100 Received: from PENCHT01.corp.atmel.com (10.168.5.161) by apsmtp01.corp.atmel.com (10.168.254.30) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 5 Jan 2016 14:46:14 +0800 Received: from penmbx02.corp.atmel.com ([fe80::b4e4:e0f6:b17c:e55f]) by PENCHT01.corp.atmel.com ([fe80::95df:d3d0:4452:28e3%12]) with mapi id 14.03.0235.001; Tue, 5 Jan 2016 14:44:55 +0800 From: "Sivanupandi, Pitchumani" To: Pedro Alves , "troth@openavr.org" , "brobecker@adacore.com" , "gdb-patches@sourceware.org" Subject: RE: [patch] Enable dwarf unwind for AVR target Date: Tue, 05 Jan 2016 06:45:00 -0000 Message-ID: References: <568A7A4F.2060504@redhat.com> In-Reply-To: <568A7A4F.2060504@redhat.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2016-01/txt/msg00045.txt.bz2 > -----Original Message----- > From: Pedro Alves [mailto:palves@redhat.com] > Sent: 04 January 2016 19:28 > To: Sivanupandi, Pitchumani ; > troth@openavr.org; brobecker@adacore.com; gdb-patches@sourceware.org > Subject: Re: [patch] Enable dwarf unwind for AVR target >=20 > On 01/04/2016 08:01 AM, Sivanupandi, Pitchumani wrote: > > - AVR_NUM_PSEUDO_REGS =3D 1, > > + AVR_DWARF2_PC_REGNUM =3D 36 /*LR*/, >=20 > It's hard to comment without some explanation for the design choices in t= he > patch, and/or some understanding of what this register is. > Seems odd that you create the register and then avr_pseudo_register_read > already returns ? Why did you need to add it? Is this a re= al > machine register? What's LR? >=20 > > + AVR_NUM_PSEUDO_REGS =3D 2, > > > > AVR_PC_REG_INDEX =3D 35, /* index into array of registers */ > > > > @@ -211,7 +213,7 @@ avr_register_name (struct gdbarch *gdbarch, int > regnum) > > "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", > > "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", > > "SREG", "SP", "PC2", > > - "pc" > > + "pc", "LR" > > }; AVR has only 32 registers. GDB maps status register, SP and PC to numbers 3= 2, 33 and 34 respectively. Dwarf debug info generated by avr-gcc denotes the return address by register 36 which is not an actual register. e.g. .debug_frame (--snip--) 00000000 00000010 ffffffff CIE Version: 1 Augmentation: "" Code alignment factor: 2 Data alignment factor: -1 Return address column: 36 DW_CFA_def_cfa: r32 ofs 3 DW_CFA_offset: r36 at cfa-2 (--snip--) The fix is to add a pseudo register (36 - AVR_DWARF2_PC_REGNUM) to gdb to m= ap return address register in .debug_frame. Register name is "LR" (link regist= er). When dwarf frame unwind asks for PC, target function should find return add= ress value (AVR_DWARF2_PC_REGNUM). Dwarf frame reader records all registers from the .debug_frame section. When gdb asks for PC value to unwind, avr_dwarf2_prev_register finds the fr= ame address recorded for AVR_DWARF2_PC_REGNUM and read value from that memory. (avr_dwarf2_prev_register implementation is similar to existing=20 avr_frame_prev_register function) I assumed pseudo register read/write for this register not mandatory for dw= arf frame unwind. So, left it with dummy implementation as of now. NOTE: * Added extern function dwarf2_frame_addr to dwarf2-frame.c to find the fra= me address for argument register from dwarf frame cache. * dwarf2 address size set to 4. Regards, Pitchumani