This started as an attempt to implement one of the missing load single
struct to one lane instructions, and by the time I figured out how get
ti right, it turned out to be simpler to just add all of the missing
ASIMD load and store instructions at the same time.  So this is a
larger patch than my previous ones.

The bulk of the changes involve handling instruction bit 24 correctly
in do_vec_load_store, by loading it into a variable called single, and
changing code to use it, calling new functions for the ldn single and
stn single instructions.  This required re-indenting some code.  The
existing ldnr support is for instructions with this bit set, so had to
be moved inside the new single support.  Since I'm implementing all of
the missing ASIMD load and store instructions here, I changed a number
of HALT_NYI calls to HALT_UNALLOC.

While doing this, I managed to find 4 bugs in the ldnr support.  In
do_vec_LDnR, there are loops using i, but only the loops in case 0
actually use i inside the loop.  Cases 1 through 3 are broken.  I
fixed this by replacing the switch with a loop, which also allows me
to remove a lot of duplicated code.  As a result, I'm removing almost
as many lines as I'm adding.  In do_vec_load_store, there is a check
that is using 0xE twice instead of 0xC and 0xE.  This is fixed by
using the new single var instead.  In the post indexed addressing mode
code, the 0xE case has 4 and 8 when it should be using 3 and 4 as
these are register counts not data sizes.  Also here, the multiply by
2 when full is set is wrong for ldnr, but this is fixed by moving it
into the new single code.

I added testcases for the ldn single and stn single instruction
support that is new, and for the ldnr instruction support that is
being fixed by this patch.  The new testcases fail without the patch,
and work with the patch.  The GCC C testsuite unexpected failures drop
from 2096 to 1701 (-395).

Jim