From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 0+i1I0jC6mJ4CSAAWB0awg (envelope-from ) for ; Wed, 03 Aug 2022 14:45:28 -0400 Received: by simark.ca (Postfix, from userid 112) id 830761EA05; Wed, 3 Aug 2022 14:45:28 -0400 (EDT) Authentication-Results: simark.ca; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=eF+o0Fbc; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 8026C1E9EB for ; Wed, 3 Aug 2022 14:45:27 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D8FF53857017 for ; Wed, 3 Aug 2022 18:45:26 +0000 (GMT) Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by sourceware.org (Postfix) with ESMTPS id 6BC343858C2D for ; Wed, 3 Aug 2022 18:45:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6BC343858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-ed1-x52c.google.com with SMTP id z22so22588504edd.6 for ; Wed, 03 Aug 2022 11:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=8UhRPTyfkILo1zOzXNDTkBcxaiIPijjBahUyLh2CD+I=; b=eF+o0Fbc792mjSJXAUEVMbzqriUHNdSGUkopuoVpyzNTCGAr1xx7NsGanH5E8swzkW nNKLg1FxzPp8lT23zOBA/4uGd62R8QJYeJVOAdozoNMlr36hkWBIcg66K2MokA8eyizx sM7qE5mWtKYEZOrxmJUHx1H/Lam84HCNzcGJOyfl5NpnvuKdwGQRik6M+asOW/1f8RXR aBb2BkHA5e9sgXbLNeHSVipF3HLryp5L7xR4O5cjGNmQHtkkI06AJgOLTWM6pqLmMYHH rgvAyvR007wIaf52m9H8DKW31wevQHmr4xubGprZ/if92OnPDNlmpBctMV/W5s0U3kpy AfXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=8UhRPTyfkILo1zOzXNDTkBcxaiIPijjBahUyLh2CD+I=; b=xFh01f96K27Wh0xCPXhzqaKAvLi1rgxH3A1/Cu5S21lMk3ZNka6w20dYmJv64m9DoV KzbrlcEWv7W3jb5rixHjL8ZNwX9ibSubJiV6msgZNHODwIj0rQKgH0bjDKsNw8U81O06 mTmdFG97Wab2m6bdsoUDs0rNgyPd6yw3PVSTq7PW097j/1PbDdbsnnT57r7hKuAVFsqp 0aIgtsNr/67/3YOGSq2vyfJ/wWteF7dqeyZxQgksp7zhTnbEOsMGIfrwjYSYpRF2F7wQ O0QTck4a9yvpQuStgw+/6aGLjdJqC95gh9HG8sa1eMSjhaAFzSKu6vCZYtI8nwMJsUyI pk0Q== X-Gm-Message-State: AJIora/q9QqmYE3kNCQaMdkCeFQ9uJ4Wq4IwF3/VxByb8S2bnE3NbFoG LeGC13KhOpk7lR172KqKMuRH6ISwY6HEpDO0USHVptHzBEA= X-Google-Smtp-Source: AGRyM1vD8gu0v4nGvBNFrrGR4RaKkJJs+fK/I/M53j2qSYImCp741uOX5cHsxzg/ZSG63ZERAXgCuz0zyGe6tURgofI= X-Received: by 2002:a05:6402:2804:b0:439:83c2:8be2 with SMTP id h4-20020a056402280400b0043983c28be2mr27633443ede.292.1659552312818; Wed, 03 Aug 2022 11:45:12 -0700 (PDT) MIME-Version: 1.0 References: <20220711175746.76137-1-hugues.delassus@sifive.com> In-Reply-To: <20220711175746.76137-1-hugues.delassus@sifive.com> From: Hugues de Lassus Date: Wed, 3 Aug 2022 11:45:03 -0700 Message-ID: Subject: [PING] [PATCH] RISC-V: fix FRM register display mask value To: gdb-patches@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hugues de Lassus Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Ping. On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus < hugues.delassus@sifive.com> wrote: > The FRM register is 3-bit long, but the top-most bit was masked off for > display, resulting in incorrectly displayed values and format strings > when FRM >= 4. > > Tested on riscv64-unknown-linux-gnu target, with FPU support. > --- > gdb/riscv-tdep.c | 2 +- > gdb/testsuite/gdb.base/float.exp | 4 +++- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 69f2123dcdb..a3afab3b998 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch > *gdbarch, > "dynamic rounding mode", > }; > int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) > - ? (d >> 5) : d) & 0x3; > + ? (d >> 5) : d) & 0x7; > > gdb_printf (file, "%sFRM:%i [%s]", > (regnum == RISCV_CSR_FCSR_REGNUM > diff --git a/gdb/testsuite/gdb.base/float.exp > b/gdb/testsuite/gdb.base/float.exp > index 62e8346928b..10c0692a976 100644 > --- a/gdb/testsuite/gdb.base/float.exp > +++ b/gdb/testsuite/gdb.base/float.exp > @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then { > gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" > } elseif [istarget "riscv*-*-*"] then { > # RISC-V may or may not have an FPU > + send_gdb "set \$frm = 7\n" > gdb_test_multiple "info float" "info float" { > - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { > + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt $" > { > pass "info float (with FPU)" > } > -re "No floating.point info available for this > processor.*$gdb_prompt $" { > pass "info float (without FPU)" > } > } > + send_gdb "set \$frm = 0\n" > } else { > gdb_test "info float" "No floating.point info available for this > processor." "info float (unknown target)" > } > -- > 2.35.1 > >