From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103032 invoked by alias); 2 Oct 2015 18:36:36 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 103023 invoked by uid 89); 2 Oct 2015 18:36:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.3 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,KAM_STOCKGEN,RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 X-HELO: smtp-out4.electric.net Received: from smtp-out4.electric.net (HELO smtp-out4.electric.net) (192.162.216.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 02 Oct 2015 18:36:35 +0000 Received: from 1Zi5C3-0000Cu-UC by out4b.electric.net with emc1-ok (Exim 4.85) (envelope-from ) id 1Zi5C3-0000Es-VG; Fri, 02 Oct 2015 11:36:31 -0700 Received: by emcmailer; Fri, 02 Oct 2015 11:36:31 -0700 Received: from [188.39.184.227] (helo=GLAEXCH3.ftdi.local) by out4b.electric.net with esmtps (TLSv1:AES128-SHA:128) (Exim 4.86) (envelope-from ) id 1Zi5C3-0000Cu-UC; Fri, 02 Oct 2015 11:36:31 -0700 Received: from GLAEXCH1.ftdi.local ([172.16.0.121]) by glaexch3 ([172.16.0.161]) with mapi id 14.01.0438.000; Fri, 2 Oct 2015 19:35:15 +0100 From: James Bowman To: "gdb-patches@sourceware.org" , "kevinb@redhat.com" Subject: RE: [PATCH, FT32] Correctly interpret function prologs Date: Fri, 02 Oct 2015 18:36:00 -0000 Message-ID: References: In-Reply-To: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Outbound-IP: 188.39.184.227 X-Env-From: james.bowman@ftdichip.com X-PolicySMART: 3094660 X-SW-Source: 2015-10/txt/msg00022.txt.bz2 Hi Kevin, Thanks for the review, I have corrected as suggested, and added a comment describing the action of the prolog subroutines. OK to apply? 2015-10-02 James Bowman * ft32-tdep.c (ft32_analyze_prologue): Add function prolog subroutine handling. diff --git a/gdb/ft32-tdep.c b/gdb/ft32-tdep.c index 00cf847..e9da23e 100644 --- a/gdb/ft32-tdep.c +++ b/gdb/ft32-tdep.c @@ -164,33 +164,76 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADD= R end_addr, CORE_ADDR next_addr; ULONGEST inst, inst2; LONGEST offset; - int regnum; + int regnum, pushreg; + struct bound_minimal_symbol msymbol; + const int first_saved_reg =3D 13; /* The first saved register. */ + /* PROLOGS are addresses of the subroutine prologs, PROLOGS[n] + is the address of __prolog_$rN. + __prolog_$rN pushes registers from 13 through n inclusive. + So for example CALL __prolog_$r15 is equivalent to: + PUSH $r13=20 + PUSH $r14=20 + PUSH $r15=20 + Note that PROLOGS[0] through PROLOGS[12] are unused. */ + CORE_ADDR prologs[32]; =20 cache->saved_regs[FT32_PC_REGNUM] =3D 0; cache->framesize =3D 0; =20 + for (regnum =3D first_saved_reg; regnum < 32; regnum++) + { + char prolog_symbol[32]; + + snprintf (prolog_symbol, sizeof (prolog_symbol), "__prolog_$r%02d", + regnum); + msymbol =3D lookup_minimal_symbol (prolog_symbol, NULL, NULL); + if (msymbol.minsym) + prologs[regnum] =3D BMSYMBOL_VALUE_ADDRESS (msymbol); + else + prologs[regnum] =3D 0; + } + if (start_addr >=3D end_addr) - return end_addr; + return end_addr; =20 cache->established =3D 0; - for (next_addr =3D start_addr; next_addr < end_addr; ) + for (next_addr =3D start_addr; next_addr < end_addr;) { inst =3D read_memory_unsigned_integer (next_addr, 4, byte_order); =20 if (FT32_IS_PUSH (inst)) { - regnum =3D FT32_R0_REGNUM + FT32_PUSH_REG (inst); + pushreg =3D FT32_PUSH_REG (inst); cache->framesize +=3D 4; - cache->saved_regs[regnum] =3D cache->framesize; + cache->saved_regs[FT32_R0_REGNUM + pushreg] =3D cache->framesize; next_addr +=3D 4; } + else if (FT32_IS_CALL (inst)) + { + for (regnum =3D first_saved_reg; regnum < 32; regnum++) + { + if ((4 * (inst & 0x3ffff)) =3D=3D prologs[regnum]) + { + for (pushreg =3D first_saved_reg; pushreg <=3D regnum; + pushreg++) + { + cache->framesize +=3D 4; + cache->saved_regs[FT32_R0_REGNUM + pushreg] =3D + cache->framesize; + } + next_addr +=3D 4; + } + } + break; + } else break; } for (regnum =3D FT32_R0_REGNUM; regnum < FT32_PC_REGNUM; regnum++) { if (cache->saved_regs[regnum] !=3D REG_UNAVAIL) - cache->saved_regs[regnum] =3D cache->framesize - cache->saved_regs[regnum= ]; + cache->saved_regs[regnum] =3D + cache->framesize - cache->saved_regs[regnum]; } cache->saved_regs[FT32_PC_REGNUM] =3D cache->framesize; =20