From: James Bowman <james.bowman@ftdichip.com>
To: Mike Frysinger <vapier@gentoo.org>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Subject: RE: [PATCH, FT32] gdb and sim support
Date: Thu, 26 Mar 2015 19:05:00 -0000 [thread overview]
Message-ID: <CA9BBF0458F83C4F9051448B941B57D117B678FA@glaexch1> (raw)
In-Reply-To: <20150326071024.GB12423@vapier>
> > +/*
> > + * FT32 is a Harvard architecture: RAM and code occupy
> > + * different address spaces.
> > + *
> > + * sim and gdb model FT32 memory by adding 0x800000 to RAM
> > + * addresses. This means that sim/gdb can treat all addresses
> > + * similarly.
> > + *
> > + * The address space looks like:
> > + *
> > + * 00000 start of code memory
> > + * 3ffff end of code memory
> > + * 800000 start of RAM
> > + * 80ffff end of RAM
> > + */
>
> do they actually occupy different address spaces ? that is to say, if you put
> address 0 into a register and try to do a data load/store, does it throw an
> exception ? or is it transparently routed to 800000 ?
At the hardware level, there are two things that have address 0: a piece
of RAM and an instruction. The CPU uses different instructions to
read RAM and instruction memory.
> Blackfin cpus are described as Harvard because it has on-chip memory that can
> only be accessed either as insn or as data, but it's a unified memory map. for
> example, if you were to execute (jump to) 0xffa00000, it'd work, but if you
> tried to do a load/store with 0xffa00000, the hardware would throw an exception.
> if you were to execute (jump to) 0xff800000, the hardware would throw an
> exception, but you could do a load/store just fine.
FT32 is closer to the AVR. Both memory spaces start at address zero.
> i'm not sure gdb or the sim generally support processors with overlapping
> memory. i.e. a $pc of 0 is completely different from a $r0 (data register) with
> the address of 0.
I believe that offsetting RAM at 800000 is the same way the AVR gdb port works.
The FT32 gdb uses the same approach. We generate a link map that declares
the RAM at address 800000. Then GDB can use a single pointer to represent
either an instruction or a RAM address. FT32's gdb interface understands
that bit 23 of an address distinguishes betweeen instruction and RAM.
This all seems to work quite well, and of course following the same
model in the simulator has made the gdb-sim interface quite straightforward.
> i tried to grab some datasheets from ftdichip.com, but (1) couldn't seem to find
> anything on the architecture (just datasheets for specific parts which covered
> more system devices than the ISA/core) and (2) it's crazy slow to download from.
I will mention this to the people at FTDI. The FT900 (which contains
the FT32 is still new).
--
James Bowman
FTDI Open Source Liaison
next prev parent reply other threads:[~2015-03-26 19:05 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-03 4:06 James Bowman
2015-02-10 6:27 ` James Bowman
2015-02-17 10:21 ` Mike Frysinger
2015-02-19 7:06 ` Mike Frysinger
[not found] ` <ORIGINAL-RELEASE-1424557036-20150219070610.GI544@vapier>
2015-02-23 10:40 ` James Bowman
2015-02-24 4:52 ` Mike Frysinger
2015-03-10 16:56 ` James Bowman
2015-03-16 8:25 ` Mike Frysinger
[not found] ` <CA9BBF0458F83C4F9051448B941B57D117234A18@glaexch1>
2015-03-19 18:52 ` Mike Frysinger
2015-03-20 2:57 ` James Bowman
2015-03-20 5:18 ` Mike Frysinger
2015-03-20 5:19 ` Mike Frysinger
2015-03-23 19:21 ` James Bowman
2015-03-26 7:10 ` Mike Frysinger
2015-03-26 19:05 ` James Bowman [this message]
2015-03-16 16:38 ` Mike Frysinger
2015-03-17 17:36 ` Joel Brobecker
2015-03-19 15:21 ` James Bowman
2015-03-19 18:54 ` Mike Frysinger
2015-03-20 3:01 ` James Bowman
2015-03-20 3:47 ` Mike Frysinger
2015-03-20 12:46 ` Joel Brobecker
2015-03-20 15:47 ` Mike Frysinger
2015-03-20 15:50 ` Joel Brobecker
2015-03-22 22:33 ` Mike Frysinger
2015-03-23 12:36 ` Joel Brobecker
2015-03-23 19:15 ` James Bowman
2015-03-23 23:04 ` Joel Brobecker
2015-03-28 6:21 ` Mike Frysinger
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