Re: [PATCH 1/3] Clear non-significant bits of address on memory access

Yao Qi
2017-12-20T09:57:11Z

"Ulrich Weigand" <uweigand@de.ibm.com> writes:

>> I am stilling thinking how to do it... alternatively, do you like the appr=
>> oach
>> that we pass 'address' to gdbarch significant_addr_bits, and teach
>> ppc32 gdbarch significant_addr_bits be aware of SPU address, that is,
>> return 64 if the top bit is one (this address is the SPU address),
>> otherwise, return 32 (this address is normal PPU address).
>
> Well, a simple workaround is to just always set significant_addr_bits
> to 64 in ppc as well. (This just doesn't matter for actual ppc addresses.)
> But that doesn't really look like a clean solution for the generic
> multi-architecture case ...

Nowadays, we strip non-significant bits in address, pass the stripped
address to target cache and to_xfer_partial. It works for aarch64, but
breaks ppc32/spu. However, in ppc32/spu case, ppu address and spu
address is mixed together, differentiated by the top bit, so the number
of significant bits of address is 64, because if we can't remove any of
them. IMO, it is reasonable to set significant_addr_bits to 64 in ppc.

I considered your suggestion that pushing address_significant call down,
below spu-multiarch target, that means, many target's to_xfer_partial
need to call address_significant, so I don't do that. Secondly, in the
way you suggested, we still pass the original address to target cache,
which works for ppu/spu, but it doesn't work for aarch64.

--
Yao (齐尧)