From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 38946 invoked by alias); 13 Nov 2017 17:32:20 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 38870 invoked by uid 89); 13 Nov 2017 17:32:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS,URIBL_RED autolearn=ham version=3.3.2 spammy=carroll, HX-Envelope-From:sk:pinskia, H*F:U*pinskia X-HELO: mail-oi0-f42.google.com Received: from mail-oi0-f42.google.com (HELO mail-oi0-f42.google.com) (209.85.218.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 13 Nov 2017 17:32:18 +0000 Received: by mail-oi0-f42.google.com with SMTP id a132so11760687oih.11 for ; Mon, 13 Nov 2017 09:32:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=WgvtCrmppGBuRxyiZdWHjPUQO9mXoY34PaQqywEAp4U=; b=O5XGAuWFcDNNDZLo0qW9UCwh+IF+KjebdH+g8fAwqPs0V2u+JlyhsG6WyXRDdrf+QE RYU5lwFdFfbMDufuVPVv82JyzYlTyf3hhxgzbgDYlMN1rSz0OZLas9V/GG7pPzV5Bcqz bP2rF5yCVMTvNos4hU+hLNN5eEe+VeZ1Ch6kxSRYr+lkYtJB5MCUGFacYQ48+O8tQPy9 N88/1ZJqVzbDhz7PJoTzZuPyNjP8oJd0HmeqNQlBVaO5yKYBGWfuSDhOSTFam90SoDjX 20taONjnPXL0s0lwWhWXpGCJVTZ/EgbNHIb4nfl5mdndtX+OkiwjLABkIj1+omEA7hNW YY5A== X-Gm-Message-State: AJaThX5PBxrQWoOvwa0vpMUuvmOw4mbWWQ5M5R1/VMbHpUMreCRY7EFO RVRFenHL+b9NjZo9eNyHkegc/0gO1MUeou/ZkQA= X-Google-Smtp-Source: AGs4zMYk8aV4oSzr+CB8Gewrmsdd4479zFzquIKSJsuSCWN4f2+onSDEcr0B4FlK/deetl9wpuZLxUBcEkHr4AopyhI= X-Received: by 10.202.60.133 with SMTP id j127mr5180562oia.67.1510594336830; Mon, 13 Nov 2017 09:32:16 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.27.6 with HTTP; Mon, 13 Nov 2017 09:32:16 -0800 (PST) In-Reply-To: <1816677702.1219332.1510594086497@mail.yahoo.com> References: <1816677702.1219332.1510594086497.ref@mail.yahoo.com> <1816677702.1219332.1510594086497@mail.yahoo.com> From: Andrew Pinski Date: Mon, 13 Nov 2017 17:32:00 -0000 Message-ID: Subject: Re: [PATCH] Modify Aarch64 prologue analyzer to accept 128-bit registers To: "pcarroll@codesourcery.com" Cc: "gdb-patches@sourceware.org" Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-11/txt/msg00235.txt.bz2 On Mon, Nov 13, 2017 at 9:28 AM, pcarroll@codesourcery.com wrote: > GDB has a routine, aarch64_analyze_prologue, that looks through a function's prologue, to see how it affects the stack. > This was changed for Bugzilla #20682 to add support for recognizing the 'stp' instruction with floating-point registers. > That patch worked when 64-bit floating-point registers are used in a function prologue. > However, it is also possible to specify 128-bit floating-point registers with the 'stp' instruction. > My patch extends that function so it works for either 64-bit or 128-bit floating-point registers. > The patch takes care of tracking the appropriate memory locations that would be affected by the use of either size of register. > > The assumption is that it is not important to know whether the register being saved is 64-bits or 128-bits in size, as long as the memory is tracked appropriately. > Instead, it is only important to know that a floating-point register (D) was being stored, rather than a normal register (X). > That behavior is unchanged. Hmm, The normal elf aarch64 ABI says only 64bits is saved. Is there another ABI which says 128bits of the SIMD register is saved? Thanks, Andrew > > 2017-11-10 Paul Carroll > > * aarch64-tdep.c (aarch64_analyze_prologue): Added support for > 128-bit registers with the 'stp' instruction.