From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8820 invoked by alias); 20 Nov 2012 13:01:52 -0000 Received: (qmail 8811 invoked by uid 22791); 20 Nov 2012 13:01:51 -0000 X-SWARE-Spam-Status: No, hits=-5.0 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_NO,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,RCVD_IN_HOSTKARMA_YE,TW_EG,TW_PV X-Spam-Check-By: sourceware.org Received: from co1ehsobe004.messaging.microsoft.com (HELO co1outboundpool.messaging.microsoft.com) (216.32.180.187) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 20 Nov 2012 13:01:32 +0000 Received: from mail140-co1-R.bigfish.com (10.243.78.241) by CO1EHSOBE010.bigfish.com (10.243.66.73) with Microsoft SMTP Server id 14.1.225.23; Tue, 20 Nov 2012 13:01:30 +0000 Received: from mail140-co1 (localhost [127.0.0.1]) by mail140-co1-R.bigfish.com (Postfix) with ESMTP id D5A4448012D; Tue, 20 Nov 2012 13:01:30 +0000 (UTC) X-Forefront-Antispam-Report: CIP:59.163.77.177;KIP:(null);UIP:(null);IPV:NLI;H:KCHJEXHC02.kpit.com;RD:59.163.77.177.static.vsnl.net.in;EFVD:NLI X-SpamScore: 2 X-BigFish: VPS2(zz936eI146fI154dI1432I111aIc8kzz1de0h1202h1d1ah1d2ahzz177df4h17326ah8275bh8275dhz2dh2a8h668h839h944hd25hf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h15d0l1155h) Received: from mail140-co1 (localhost.localdomain [127.0.0.1]) by mail140-co1 (MessageSwitch) id 1353416488691727_27888; Tue, 20 Nov 2012 13:01:28 +0000 (UTC) Received: from CO1EHSMHS027.bigfish.com (unknown [10.243.78.236]) by mail140-co1.bigfish.com (Postfix) with ESMTP id A583D9A027C; Tue, 20 Nov 2012 13:01:28 +0000 (UTC) Received: from KCHJEXHC02.kpit.com (59.163.77.177) by CO1EHSMHS027.bigfish.com (10.243.66.37) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 20 Nov 2012 13:01:24 +0000 Received: from KCHJEXMB02.kpit.com ([169.254.2.53]) by KCHJEXHC02.kpit.com ([172.10.15.74]) with mapi id 14.02.0247.003; Tue, 20 Nov 2012 18:31:01 +0530 From: Kaushik Phatak To: Joel Brobecker CC: Yao Qi , "gdb-patches@sourceware.org" Subject: RE: [RFA 3/5] New port: CR16: gdb port Date: Tue, 20 Nov 2012 13:01:00 -0000 Message-ID: References: <507279C7.8080401@codesourcery.com> <20121022224107.GB3713@adacore.com> <20121023135502.GA3555@adacore.com> <20121115174313.GC3790@adacore.com> In-Reply-To: <20121115174313.GC3790@adacore.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: kpitcummins.com Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-11/txt/msg00533.txt.bz2 Hi Joel, Thanks for another round of detailed review. I have tried to incorporate as= =20 much of this review in the attached version of this patch. Please see below my comments and the updated cr16 gdb patch. I have not att= ached the bfd part as this is unchanged as of now. > Both bfd and opcode bits needs to be approved before the GDB part > can go ahead. Ok, understood. Once I clear up couple of points related to bfd functions used in this port, I will resubmit it to binutils for approval. > +#include "solib-svr4.h" Is this include really needed Removed this from cr16-linux-tdep.c and cr16-tdep.c. > return reg_names[regnr]; > Would you mind adding an assertion that REGNR is=20 Added gdb_assert inside the register_name function. > move the array outside of the function, and to use a static assertion. Moved the array outside and added static_gdb_assert to both my files to che= ck the array using ARRAY_SIZE macro. > + case SIM_CR16_CFG_REGNUM: > + return builtin_type (gdbarch)->builtin_uint32; > + break; > Why not merge all blocks that return builtin_int32? Yes, that would make it little more cleaner. Have merged them as suggested. > + allWords =3D > Can you please void using the mixed-cap style for variables? This variable along with currInsn suffer from the same problem. However, th= ey have been borrowed from existing code from opcodes/cr16-dis.c May I leave them here as is for now as it is used at several places in cr16= -dis.c? > > + ULONGEST ra_prev; > It looks like ra_prev could be declared in the only else if block where > it is actually used. Moved this declaration inside the else if block. > And reg_size appears to be unused. Removed this line of code. I had borrowed it from Renesas RX port and it seems to be unused there as well, http://sourceware.org/ml/gdb-patches/2009-12/msg00038.html > I don't understand the comment... Removed this comment, was added at very primitive stage of the port. Not re= quired=20 now. >> + PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ > The generic_save_dummy_frame_tos function was deleted in 2004... Yes, this part was copy pasted from elsewhere. I have removed it in this ve= rsion. > add the "(C)" after Copyright > /* Note:PC Can you add a space after the colon? > Can you add a space after "/*",=20 > you should break before the operator, not after. > Can you remove the extra braces? > Can you also remove the unnecessary curly braces above, please? > Trailing spaces here... > Unnecessary braces... Fixed all the formatting related comments mentioned above.=20 I should have caught few of them myself, but thanks. > ? Looks like you have all these files twice in the patch you sent? > I'll assume a pilot error an not review the second instances. I am quite sure I had extracted the patch only once and attached it as is.= =20 Anyway, thanks again for spending time on this. Regards, Kaushik --- 2012-11-20 Kaushik Phatak gdb/Changelog * configure.tgt: Handle cr16*-*-*linux and cr16*-*-*. * cr16-linux-tdep.c: New file. * cr16-tdep.c: New file. * cr16-tdep.h: New file. =09 --- ./gdb_src.orig/gdb/configure.tgt 2012-08-02 01:18:44.000000000 +0530 +++ ./gdb_src/gdb/configure.tgt 2012-10-23 15:09:24.000000000 +0530 @@ -116,6 +116,18 @@ bfin-*-*) gdb_sim=3D../sim/bfin/libsim.a ;; =20 +cr16*-*-*linux) + # Target: CR16 processor + gdb_target_obs=3D"cr16-tdep.o cr16-linux-tdep.o linux-tdep.o" + gdb_sim=3D../sim/cr16/libsim.a + ;; + +cr16*-*-*) + # Target: CR16 processor + gdb_target_obs=3D"cr16-tdep.o" + gdb_sim=3D../sim/cr16/libsim.a + ;; + cris*) # Target: CRIS gdb_target_obs=3D"cris-tdep.o solib-svr4.o" --- ./gdb_src.orig/gdb/cr16-linux-tdep.c 1970-01-01 05:30:00.000000000 +0530 +++ ./gdb_src/gdb/cr16-linux-tdep.c 2012-11-20 15:19:48.000000000 +0530 @@ -0,0 +1,108 @@ +/* Target-dependent code for GNU/Linux on the Sitel CR16 processors. + + Copyright (C) 2012 Free Software Foundation, Inc. + + Contributed by Kaushik Phatak (kaushik.phatak@kpitcummins.com) + KPIT Cummins Infosystems Limited, Pune India. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . = */ + +#include "defs.h" +#include "osabi.h" +#include "elf-bfd.h" +#include "elf/cr16.h" +#include "linux-tdep.h" +#include "solib-svr4.h" +#include "symtab.h" +#include "cr16-tdep.h" + +/* Number of registers available for Linux targets */ +#define CR16_LINUX_NUM_REGS 21 + +/* The breakpoint instruction used by uClinux target */ +static const gdb_byte breakpoint_uclinux[] =3D { 0xC7, 0x00 }; + +static const char *const reg_names[] =3D +{ + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "ra", + "psr", + "pc", + "r0r1_orig", + "intbase", + "usp", + "cfg" +}; + +/* Verify register array size is within hardware register limit. */ + +gdb_static_assert (ARRAY_SIZE (reg_names) <=3D CR16_LINUX_NUM_REGS); + +/* Implement the "register_name" gdbarch method. */ + +static const char * +cr16_linux_register_name (struct gdbarch *gdbarch, int regnr) +{ + gdb_assert (regnr >=3D 0 && regnr < CR16_LINUX_NUM_REGS); + return reg_names[regnr]; +} + +/* OS specific initialization of gdbarch. */ + +static void +cr16_uclinux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); + + linux_init_abi (info, gdbarch); + + set_gdbarch_num_regs (gdbarch, CR16_LINUX_NUM_REGS); + set_gdbarch_register_name (gdbarch, cr16_linux_register_name); + + /* The opcode of excp bpt is 0x00C8, however for uclinux we will + use the excp flg (0x00C7) to insert a breakpoint. The excp bpt + requires external hardware support for breakpoints to work on + CR16 target. Software based breakpoints are implemented in the + kernel using excp flg and tested on the SC14452 target. Use + 0x00C7 with gdbserver/kernel and 0x00C8 for sim/ELF. We + represent the breakpoint in little endian format since CR16 + supports only little endian. */ + tdep->breakpoint =3D breakpoint_uclinux; + +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +extern initialize_file_ftype _initialize_cr16_linux_tdep; + +void +_initialize_cr16_linux_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_cr16, 0, GDB_OSABI_LINUX, + cr16_uclinux_init_abi); +} --- ./gdb_src.orig/gdb/cr16-tdep.c 1970-01-01 05:30:00.000000000 +0530 +++ ./gdb_src/gdb/cr16-tdep.c 2012-11-20 15:19:40.000000000 +0530 @@ -0,0 +1,894 @@ +/* Target-dependent code for the Sitel CR16 for GDB, the GNU debugger. +=20 + Copyright (C) 2012 Free Software Foundation, Inc. +=20 + Contributed by Kaushik Phatak (kaushik.phatak@kpitcummins.com) + KPIT Cummins Infosystems Limited, Pune India. + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. +=20 + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. +=20 + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "defs.h" +#include "arch-utils.h" +#include "prologue-value.h" +#include "target.h" +#include "regcache.h" +#include "opcode/cr16.h" +#include "dis-asm.h" +#include "gdbtypes.h" +#include "frame.h" +#include "frame-unwind.h" +#include "frame-base.h" +#include "value.h" +#include "gdbcore.h" +#include "dwarf2-frame.h" +#include "gdb/sim-cr16.h" +#include "elf/cr16.h" +#include "elf-bfd.h" +#include "osabi.h" +#include "cr16-tdep.h" + +/* Number of registers available for ELF targets. */ +#define CR16_NUM_REGS 22 + +/* The breakpoint instruction used with sim for ELF targets. */ +static const gdb_byte breakpoint_elf[] =3D { 0xC8, 0x00 }; + +/* Certain important register numbers. */ +enum +{ + CR16_R0_REGNUM =3D 0, + CR16_R7_REGNUM =3D 7, + CR16_R12_REGNUM =3D 12, + CR16_FP_REGNUM =3D 13, + CR16_RA_REGNUM =3D 14, + CR16_SP_REGNUM =3D 15, + CR16_PC_REGNUM =3D 16, +}; + +/* This structure holds the results of a prologue analysis. */ +struct cr16_prologue +{ + /* The offset from the frame base to the stack pointer --- always + zero or negative. + + Calling this a "size" is a bit misleading, but given that the + stack grows downwards, using offsets for everything keeps one + from going completely sign-crazy: you never change anything's + sign for an ADD instruction; always change the second operand's + sign for a SUB instruction; and everything takes care of + itself. */ + int frame_size; + + /* Non-zero if this function has initialized the frame pointer from + the stack pointer, zero otherwise. */ + int has_frame_ptr; + + /* If has_frame_ptr is non-zero, this is the offset from the frame + base to where the frame pointer points. This is always zero or + negative. */ + int frame_ptr_offset; + + /* The address of the first instruction at which the frame has been + set up and the arguments are where the debug info says they are + --- as best as we can tell. */ + CORE_ADDR prologue_end; + + /* reg_offset[R] is the offset from the CFA at which register R is + saved, or 1 if register R has not been saved. (Real values are + always zero or negative.) */ + int reg_offset[CR16_NUM_REGS]; +}; + +/* Hardware register name declaration. */ +static const char *const reg_names[] =3D +{ + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "ra", + "sp", + "pc", + "isp", + "usp", + "intbase", + "psr", + "cfg" +}; + +/* Verify register array size is within hardware register limit. */ + +gdb_static_assert (ARRAY_SIZE (reg_names) <=3D CR16_NUM_REGS); + +/* Implement the "register_name" gdbarch method. */ + +static const char * +cr16_register_name (struct gdbarch *gdbarch, int regnr) +{ + gdb_assert (regnr >=3D 0 && regnr < CR16_NUM_REGS); + return reg_names[regnr]; +} + +/* Implement the "register_type" gdbarch method. */ + +static struct type * +cr16_register_type (struct gdbarch *gdbarch, int reg_nr) +{ + switch (reg_nr) + { + case CR16_PC_REGNUM: /* Note: PC in CR16 is of 24 bits. */ + return builtin_type (gdbarch)->builtin_func_ptr; + + case CR16_RA_REGNUM: /* Return address reg. */ + return builtin_type (gdbarch)->builtin_data_ptr; + break; + + case CR16_FP_REGNUM: /* Frame Pointer reg. */ + case CR16_SP_REGNUM: /* Stack Pointer reg. */ + return builtin_type (gdbarch)->builtin_data_ptr; + break; + + case SIM_CR16_ISP_REGNUM: + case SIM_CR16_USP_REGNUM: + case SIM_CR16_INTBASE_REGNUM: + case SIM_CR16_PSR_REGNUM: + case SIM_CR16_CFG_REGNUM: + return builtin_type (gdbarch)->builtin_int32; + break; + + case SIM_CR16_R0_REGNUM: + case SIM_CR16_R1_REGNUM: + case SIM_CR16_R2_REGNUM: + case SIM_CR16_R3_REGNUM: + case SIM_CR16_R4_REGNUM: + case SIM_CR16_R5_REGNUM: + case SIM_CR16_R6_REGNUM: + case SIM_CR16_R7_REGNUM: + case SIM_CR16_R8_REGNUM: + case SIM_CR16_R9_REGNUM: + case SIM_CR16_R10_REGNUM: + case SIM_CR16_R11_REGNUM: + return builtin_type (gdbarch)->builtin_int16; + break; + + case SIM_CR16_R12_REGNUM: + return builtin_type (gdbarch)->builtin_int32; + break; + + default: + return builtin_type (gdbarch)->builtin_int32; + break; + } +} + +/* Function for finding saved registers in a 'struct pv_area'; this + function is passed to pv_area_scan. + + If VALUE is a saved register, ADDR says it was saved at a constant + offset from the frame base, and SIZE indicates that the whole + register was saved, record its offset. */ + +static void +check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t val= ue) +{ + struct cr16_prologue *result =3D (struct cr16_prologue *) result_untyped; + + if (value.kind =3D=3D pvk_register + && value.k =3D=3D 0 + && pv_is_register (addr, CR16_SP_REGNUM) + && size =3D=3D register_size (target_gdbarch, value.reg)) + result->reg_offset[value.reg] =3D addr.k; +} + +/* Define a "handle" struct for fetching the next opcode. */ + +struct cr16_get_opcode_byte_handle +{ + CORE_ADDR pc; +}; + +/* Analyze a prologue starting at START_PC, going no further than + LIMIT_PC. Fill in RESULT as appropriate. */ + +static void +cr16_analyze_prologue (CORE_ADDR start_pc, + CORE_ADDR limit_pc, struct cr16_prologue *result) +{ + CORE_ADDR pc, next_pc; + gdb_byte insn_byte1, insn_byte2; + int rn; + int length; + pv_t reg[CR16_NUM_REGS]; + struct pv_area *stack; + struct cleanup *back_to; + CORE_ADDR after_last_frame_setup_insn =3D start_pc; + int is_decoded; + + memset (result, 0, sizeof (*result)); + + for (rn =3D 0; rn < CR16_NUM_REGS; rn++) + { + reg[rn] =3D pv_register (rn, 0); + result->reg_offset[rn] =3D 1; + } + + stack =3D make_pv_area (CR16_SP_REGNUM, gdbarch_addr_bit (target_gdbarch= )); + back_to =3D make_cleanup_free_pv_area (stack); + + pc =3D start_pc; + while (pc < limit_pc) + { + gdb_byte buf[6]; + + /* Read 6 bytes, max 48 bit opcode. */ + target_read_memory (pc, buf, 6); + words[0] =3D buf[1] << 8 | buf[0]; + words[1] =3D buf[3] << 8 | buf[2]; + words[2] =3D buf[5] << 8 | buf[4]; + allWords =3D (((ULONGLONG) words[0] << 32) + + ((ULONGLONG) words[1] << 16) + + words[2]); + + /* Find a matching opcode in table. + Nonzero means instruction has a match. */ + is_decoded =3D match_opcode (); + make_instruction (); + length =3D currInsn.size; + next_pc =3D pc + length; + insn_byte1 =3D (words[0] >> 8) & 0xFF; + + /* If PUSH, then save RA and other regs. */ + if (insn_byte1 =3D=3D 0x01) + { + int r1, r2; + int r; + + insn_byte2 =3D words[0]; + + if (insn_byte2 & 0x80) + { + reg[CR16_SP_REGNUM] =3D pv_add_constant (reg[CR16_SP_REGNUM], -4); + pv_area_store (stack, reg[CR16_SP_REGNUM], 4, + reg[CR16_RA_REGNUM]); + } + /* Start Register=3Dr1, 3 bit imm count=3Dr2. */ + r1 =3D insn_byte2 & 0x0F; + r2 =3D ((insn_byte2 & 0x70) >> 4); + r2 =3D r2 + r1 + 1; + + for (r =3D r1; r < r2; r++) + { + if (r >=3D CR16_R12_REGNUM) + { + reg[CR16_SP_REGNUM] =3D + pv_add_constant (reg[CR16_SP_REGNUM], -4); + pv_area_store (stack, reg[CR16_SP_REGNUM], 4, reg[r]); + r++; + } + else + { + reg[CR16_SP_REGNUM] =3D + pv_add_constant (reg[CR16_SP_REGNUM], -2); + pv_area_store (stack, reg[CR16_SP_REGNUM], 2, reg[r]); + } + } + after_last_frame_setup_insn =3D next_pc; + } + /* Add constant to SP. */ + else if (insn_byte1 =3D=3D 0x60) + { + int rdst; + signed short addend; + + insn_byte2 =3D words[0]; + rdst =3D insn_byte2 & 0x0F; + if (rdst =3D=3D CR16_SP_REGNUM) + { + if (length =3D=3D 2) + { + addend =3D (insn_byte2 & 0xF0) >> 4; + reg[rdst] =3D pv_add_constant (reg[rdst], addend); + } + if (length =3D=3D 4) + { + addend =3D words[1]; + reg[rdst] =3D pv_add_constant (reg[rdst], addend); + } + after_last_frame_setup_insn =3D next_pc; + } + } + /* Check for MOVD insn. */ + else if (insn_byte1 =3D=3D 0x55) + { + int rdst, rsrc; + + insn_byte2 =3D words[0]; + rsrc =3D (insn_byte2 & 0xF0) >> 4; + rdst =3D (insn_byte2 & 0x0F); + reg[rdst] =3D reg[rsrc]; + if (rsrc =3D=3D CR16_SP_REGNUM && rdst =3D=3D CR16_FP_REGNUM) + after_last_frame_setup_insn =3D next_pc; + } + else if (((insn_byte1 >> 4) & 0x0F) =3D=3D 0xd) + { + /* This moves an argument register to the stack. Don't + record it, but allow it to be a part of the prologue. */ + after_last_frame_setup_insn =3D next_pc; + } + else + break; /* Terminate the prologue scan. */ + + pc =3D next_pc; + } + + /* Is the frame size (offset, really) a known constant? */ + if (pv_is_register (reg[CR16_SP_REGNUM], CR16_SP_REGNUM)) + result->frame_size =3D reg[CR16_SP_REGNUM].k; + + /* Was the frame pointer initialized? */ + if (pv_is_register (reg[CR16_FP_REGNUM], CR16_SP_REGNUM)) + { + result->has_frame_ptr =3D 1; + result->frame_ptr_offset =3D reg[CR16_FP_REGNUM].k; + } + + /* Record where all the registers were saved. */ + pv_area_scan (stack, check_for_saved, (void *) result); + + result->prologue_end =3D after_last_frame_setup_insn; + do_cleanups (back_to); +} + + +/* Implement the "skip_prologue" gdbarch method. */ + +static CORE_ADDR +cr16_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + const char *name; + CORE_ADDR func_addr, func_end; + struct cr16_prologue p; + + /* Try to find the extent of the function that contains PC. */ + if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) + return pc; + + cr16_analyze_prologue (pc, func_end, &p); + return p.prologue_end; +} + +/* Given a frame described by THIS_FRAME, decode the prologue of its + associated function if there is not cache entry as specified by + THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and + return that struct as the value of this function. */ + +static struct cr16_prologue * +cr16_analyze_frame_prologue (struct frame_info *this_frame, + void **this_prologue_cache) +{ + if (*this_prologue_cache) + return *this_prologue_cache; + + CORE_ADDR func_start, stop_addr; + + *this_prologue_cache =3D FRAME_OBSTACK_ZALLOC (struct cr16_prologue); + func_start =3D get_frame_func (this_frame); + stop_addr =3D get_frame_pc (this_frame); + + /* If we couldn't find any function containing the PC, then + just initialize the prologue cache, but don't do anything. */ + if (!func_start) + stop_addr =3D func_start; + + cr16_analyze_prologue (func_start, stop_addr, *this_prologue_cache); + + return *this_prologue_cache; +} + +/* Given the next frame and a prologue cache, return this frame's + base. */ + +static CORE_ADDR +cr16_frame_base (struct frame_info *this_frame, void **this_prologue_cache) +{ + struct cr16_prologue *p + =3D cr16_analyze_frame_prologue (this_frame, this_prologue_cache); + + /* In functions that use alloca, the distance between the stack + pointer and the frame base varies dynamically, so we can't use + the SP plus static information like prologue analysis to find the + frame base. However, such functions must have a frame pointer, + to be able to restore the SP on exit. So whenever we do have a + frame pointer, use that to find the base. */ + if (p->has_frame_ptr) + { + CORE_ADDR fp =3D get_frame_register_unsigned (this_frame, CR16_FP_RE= GNUM); + return fp - p->frame_ptr_offset; + } + else + { + CORE_ADDR sp =3D get_frame_register_unsigned (this_frame, CR16_SP_RE= GNUM); + return sp - p->frame_size; + } +} + +/* Implement the "frame_this_id" method for unwinding frames. */ + +static void +cr16_frame_this_id (struct frame_info *this_frame, + void **this_prologue_cache, struct frame_id *this_id) +{ + *this_id =3D + frame_id_build (cr16_frame_base (this_frame, this_prologue_cache), + get_frame_func (this_frame)); +} + +/* Implement the "frame_prev_register" method for unwinding frames. */ + +static struct value * +cr16_frame_prev_register (struct frame_info *this_frame, + void **this_prologue_cache, int regnum) +{ + struct cr16_prologue *p =3D + cr16_analyze_frame_prologue (this_frame, this_prologue_cache); + CORE_ADDR frame_base =3D cr16_frame_base (this_frame, this_prologue_cach= e); + + if (regnum =3D=3D CR16_SP_REGNUM) + return frame_unwind_got_constant (this_frame, regnum, frame_base); + + /* The call instruction has saved the return address on the RA + register, CR16_R13_REGNUM. So, we need not adjust anything + directly. We will analyze prologue as this RA register is + pushed onto stack for further leaf function calls to work. */ + else if (regnum =3D=3D CR16_PC_REGNUM) + { + ULONGEST ra_prev; + + ra_prev =3D frame_unwind_register_unsigned (this_frame, CR16_RA_REGN= UM); + ra_prev =3D ra_prev << 1; + return frame_unwind_got_constant (this_frame, CR16_PC_REGNUM, ra_pre= v); + } + + /* If prologue analysis says we saved this register somewhere, + return a description of the stack slot holding it. */ + else if (p->reg_offset[regnum] !=3D 1) + return frame_unwind_got_memory (this_frame, regnum, + frame_base + p->reg_offset[regnum]); + + /* Otherwise, presume we haven't changed the value of this + register, and get it from the next frame. */ + else + return frame_unwind_got_register (this_frame, regnum, regnum); +} + +static const struct frame_unwind cr16_frame_unwind =3D +{ + NORMAL_FRAME, + default_frame_unwind_stop_reason, + cr16_frame_this_id, + cr16_frame_prev_register, + NULL, + default_frame_sniffer +}; + +/* Implement the "unwind_pc" gdbarch method. */ + +static CORE_ADDR +cr16_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) +{ + CORE_ADDR pc; + + pc =3D frame_unwind_register_unsigned (this_frame, CR16_PC_REGNUM); + return pc; +} + +/* Implement the "unwind_sp" gdbarch method. */ + +static CORE_ADDR +cr16_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) +{ + CORE_ADDR sp; + + sp =3D frame_unwind_register_unsigned (this_frame, CR16_SP_REGNUM); + return sp; +} + +/* Implement the "dummy_id" gdbarch method. */ + +static struct frame_id +cr16_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) +{ + return + frame_id_build (get_frame_register_unsigned (this_frame, CR16_SP_REGNU= M), + get_frame_pc (this_frame)); +} + +/* Implement the "push_dummy_call" gdbarch method. */ + +static CORE_ADDR +cr16_push_dummy_call (struct gdbarch *gdbarch, struct value *function, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) +{ + enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch); + int write_pass; + int sp_off =3D 0; + CORE_ADDR cfa; + int num_register_candidate_args; + + struct type *func_type =3D value_type (function); + + /* Dereference function pointer types. */ + while (TYPE_CODE (func_type) =3D=3D TYPE_CODE_PTR) + func_type =3D TYPE_TARGET_TYPE (func_type); + + /* The end result had better be a function or a method. */ + gdb_assert (TYPE_CODE (func_type) =3D=3D TYPE_CODE_FUNC + || TYPE_CODE (func_type) =3D=3D TYPE_CODE_METHOD); + + /* Functions with a variable number of arguments have all of their + variable arguments and the last non-variable argument passed + on the stack. + + Otherwise, we can pass up to four arguments on the stack. + + Once computed, we leave this value alone. I.e. we don't update + it in case of a struct return going in a register or an argument + requiring multiple registers, etc. We rely instead on the value + of the ``arg_reg'' variable to get these other details correct. */ + + if (TYPE_VARARGS (func_type)) + num_register_candidate_args =3D TYPE_NFIELDS (func_type) - 1; + else + num_register_candidate_args =3D 4; + + /* We make two passes; the first does the stack allocation, + the second actually stores the arguments. */ + for (write_pass =3D 0; write_pass <=3D 1; write_pass++) + { + int i; + int arg_reg =3D CR16_R0_REGNUM; + + if (write_pass) + sp =3D align_down (sp - sp_off, 4); + sp_off =3D 0; + + if (struct_return) + { + struct type *return_type =3D TYPE_TARGET_TYPE (func_type); + + gdb_assert (TYPE_CODE (return_type) =3D=3D TYPE_CODE_STRUCT + || TYPE_CODE (func_type) =3D=3D TYPE_CODE_UNION); + + if (TYPE_LENGTH (return_type) > 16 + || TYPE_LENGTH (return_type) % 4 !=3D 0) + { + if (write_pass) + regcache_cooked_write_unsigned (regcache, CR16_R12_REGNUM, + struct_addr); + } + } + + /* Push the arguments. */ + for (i =3D 0; i < nargs; i++) + { + struct value *arg =3D args[i]; + const gdb_byte *arg_bits =3D value_contents_all (arg); + struct type *arg_type =3D check_typedef (value_type (arg)); + ULONGEST arg_size =3D TYPE_LENGTH (arg_type); + + if (i =3D=3D 0 && struct_addr !=3D 0 && !struct_return + && TYPE_CODE (arg_type) =3D=3D TYPE_CODE_PTR + && extract_unsigned_integer (arg_bits, 4, + byte_order) =3D=3D struct_addr) + { + /* This argument represents the address at which C++ (and + possibly other languages) store their return value. + Put this value in R12. */ + if (write_pass) + regcache_cooked_write_unsigned (regcache, CR16_R12_REGNUM, + struct_addr); + } + else if (TYPE_CODE (arg_type) !=3D TYPE_CODE_STRUCT + && TYPE_CODE (arg_type) !=3D TYPE_CODE_UNION) + { + /* Argument is a scalar. */ + if (arg_size =3D=3D 8) + { + if (i < num_register_candidate_args + && arg_reg <=3D CR16_R7_REGNUM - 1) + { + /* If argument registers are going to be used to pass + an 8 byte scalar, the ABI specifies that two registers + must be available. */ + if (write_pass) + { + regcache_cooked_write_unsigned (regcache, arg_reg, + extract_unsigned_integer + (arg_bits, 4, + byte_order)); + regcache_cooked_write_unsigned (regcache, + arg_reg + 1, + extract_unsigned_integer + (arg_bits + 4, 4, + byte_order)); + } + arg_reg +=3D 2; + } + else + { + sp_off =3D align_up (sp_off, 4); + /* Otherwise, pass the 8 byte scalar on the stack. */ + if (write_pass) + write_memory (sp + sp_off, arg_bits, 8); + sp_off +=3D 8; + } + } + else + { + ULONGEST u; + + gdb_assert (arg_size <=3D 4); + + u =3D extract_unsigned_integer (arg_bits, arg_size, byte_order); + + if (i < num_register_candidate_args + && arg_reg <=3D CR16_R7_REGNUM) + { + if (write_pass) + regcache_cooked_write_unsigned (regcache, arg_reg, u); + arg_reg +=3D 1; + } + else + { + int p_arg_size =3D 4; + + if (TYPE_PROTOTYPED (func_type) + && i < TYPE_NFIELDS (func_type)) + { + struct type *p_arg_type =3D + TYPE_FIELD_TYPE (func_type, i); + p_arg_size =3D TYPE_LENGTH (p_arg_type); + } + + sp_off =3D align_up (sp_off, p_arg_size); + + if (write_pass) + write_memory_unsigned_integer (sp + sp_off, + p_arg_size, byte_order, + u); + sp_off +=3D p_arg_size; + } + } + } + else + { + /* Argument is a struct or union. Pass as much of the struct + in registers, as possible. Pass the rest on the stack. */ + while (arg_size > 0) + { + if (i < num_register_candidate_args + && arg_reg <=3D CR16_R7_REGNUM + && arg_size <=3D 4 * (CR16_R7_REGNUM - arg_reg + 1) + && arg_size % 4 =3D=3D 0) + { + int len =3D min (arg_size, 4); + + if (write_pass) + regcache_cooked_write_unsigned (regcache, arg_reg, + extract_unsigned_integer + (arg_bits, len, + byte_order)); + arg_bits +=3D len; + arg_size -=3D len; + arg_reg++; + } + else + { + sp_off =3D align_up (sp_off, 4); + if (write_pass) + write_memory (sp + sp_off, arg_bits, arg_size); + sp_off +=3D align_up (arg_size, 4); + arg_size =3D 0; + } + } + } + } + } + + /* Keep track of the stack address prior to pushing the return address. + This is the value that we'll return. */ + cfa =3D sp; + + /* Push the return address. */ + sp =3D sp - 4; + write_memory_unsigned_integer (sp, 4, byte_order, bp_addr); + + /* Update the stack pointer. */ + regcache_cooked_write_unsigned (regcache, CR16_SP_REGNUM, sp); + + return cfa; +} + +/* Implement the "return_value" gdbarch method. */ + +static enum return_value_convention +cr16_return_value (struct gdbarch *gdbarch, + struct type *func_type, + struct type *valtype, + struct regcache *regcache, + gdb_byte * readbuf, const gdb_byte * writebuf) +{ + enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch); + ULONGEST valtype_len =3D TYPE_LENGTH (valtype); + + if (TYPE_LENGTH (valtype) > 16 + || ((TYPE_CODE (valtype) =3D=3D TYPE_CODE_STRUCT + || TYPE_CODE (valtype) =3D=3D TYPE_CODE_UNION) + && TYPE_LENGTH (valtype) % 4 !=3D 0)) + return RETURN_VALUE_STRUCT_CONVENTION; + + if (readbuf) + { + ULONGEST u; + int argreg =3D CR16_R0_REGNUM; + int offset =3D 0; + + while (valtype_len > 0) + { + int len =3D min (valtype_len, 4); + + regcache_cooked_read_unsigned (regcache, argreg, &u); + store_unsigned_integer (readbuf + offset, len, byte_order, u); + valtype_len -=3D len; + offset +=3D len; + argreg++; + } + } + + if (writebuf) + { + ULONGEST u; + int argreg =3D CR16_R0_REGNUM; + int offset =3D 0; + + while (valtype_len > 0) + { + int len =3D min (valtype_len, 4); + + u =3D extract_unsigned_integer (writebuf + offset, len, byte_order); + regcache_cooked_write_unsigned (regcache, argreg, u); + valtype_len -=3D len; + offset +=3D len; + argreg++; + } + } + + return RETURN_VALUE_REGISTER_CONVENTION; +} + +/* Implement the "breakpoint_from_pc" gdbarch method. */ + +static const gdb_byte * +cr16_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, + int *lenptr) +{ + /* We use different breakpoint instructions for ELF and uClinux. + See cr16-linux-tdep.c for more details. */ + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); + + *lenptr =3D 2; + if (tdep =3D=3D NULL || tdep->breakpoint =3D=3D NULL) + return breakpoint_elf; + + return tdep->breakpoint; +} + +/* Allocate and initialize a gdbarch object. */ + +static struct gdbarch * +cr16_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch *gdbarch; + struct gdbarch_tdep *tdep; + int elf_flags; + + /* Extract the elf_flags if available. */ + if (info.abfd !=3D NULL + && bfd_get_flavour (info.abfd) =3D=3D bfd_target_elf_flavour) + elf_flags =3D elf_elfheader (info.abfd)->e_flags; + else + elf_flags =3D 0; + + /* Try to find the architecture in the list of already defined + architectures. */ + for (arches =3D gdbarch_list_lookup_by_info (arches, &info); + arches !=3D NULL; + arches =3D gdbarch_list_lookup_by_info (arches->next, &info)) + { + if (gdbarch_tdep (arches->gdbarch)->elf_flags !=3D elf_flags) + continue; + + return arches->gdbarch; + } + /* None found, create a new architecture from the information + provided. */ + tdep =3D (struct gdbarch_tdep *) xcalloc (1, sizeof (struct gdbarch_tdep= )); + tdep->elf_flags =3D elf_flags; + gdbarch =3D gdbarch_alloc (&info, tdep); + + set_gdbarch_num_pseudo_regs (gdbarch, 0); + set_gdbarch_num_regs (gdbarch, CR16_NUM_REGS); + set_gdbarch_register_name (gdbarch, cr16_register_name); + set_gdbarch_register_type (gdbarch, cr16_register_type); + set_gdbarch_pc_regnum (gdbarch, CR16_PC_REGNUM); + set_gdbarch_sp_regnum (gdbarch, CR16_SP_REGNUM); + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + set_gdbarch_decr_pc_after_break (gdbarch, 2); + set_gdbarch_breakpoint_from_pc (gdbarch, cr16_breakpoint_from_pc); + set_gdbarch_skip_prologue (gdbarch, cr16_skip_prologue); + set_gdbarch_print_insn (gdbarch, print_insn_cr16); + set_gdbarch_unwind_pc (gdbarch, cr16_unwind_pc); + set_gdbarch_unwind_sp (gdbarch, cr16_unwind_sp); + + /* Methods for saving / extracting a dummy frame's ID. */ + set_gdbarch_dummy_id (gdbarch, cr16_dummy_id); + set_gdbarch_push_dummy_call (gdbarch, cr16_push_dummy_call); + /* Target builtin data types. */ + set_gdbarch_char_signed (gdbarch, 8); + set_gdbarch_short_bit (gdbarch, 16); + set_gdbarch_int_bit (gdbarch, 16); + set_gdbarch_long_bit (gdbarch, 32); + set_gdbarch_long_long_bit (gdbarch, 64); + set_gdbarch_float_bit (gdbarch, 32); + + set_gdbarch_ptr_bit (gdbarch, 32); + set_gdbarch_float_format (gdbarch, floatformats_ieee_single); + set_gdbarch_double_bit (gdbarch, 64); + set_gdbarch_long_double_bit (gdbarch, 64); + set_gdbarch_double_format (gdbarch, floatformats_ieee_double); + set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); + + frame_unwind_append_unwinder (gdbarch, &cr16_frame_unwind); + set_gdbarch_return_value (gdbarch, cr16_return_value); + + /* Hook in ABI-specific overrides, if they have been registered. */ + gdbarch_init_osabi (info, gdbarch); + + return gdbarch; + +} + +/* -Wmissing-prototypes. */ +extern initialize_file_ftype _initialize_cr16_tdep; + +/* Register the above initialization routine. */ + +void +_initialize_cr16_tdep (void) +{ + register_gdbarch_init (bfd_arch_cr16, cr16_gdbarch_init); +} --- ./gdb_src.orig/gdb/cr16-tdep.h 1970-01-01 05:30:00.000000000 +0530 +++ ./gdb_src/gdb/cr16-tdep.h 2012-11-16 10:04:08.000000000 +0530 @@ -0,0 +1,32 @@ +/* GNU/Linux on CR16 target support. + Copyright (C) 2012 Free Software Foundation, Inc. + + Contributed by Kaushik Phatak (kaushik.phatak@kpitcummins.com) + KPIT Cummins Infosystems Limited, Pune India. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . = */ + + +/* Target-dependent structure in gdbarch. */ + +struct gdbarch_tdep +{ + /* The ELF header flags specify the multilib used. */ + int elf_flags; + + /* Breakpoint instruction. */ + const gdb_byte *breakpoint; +};=09