[PATCH v2 06/10] Add Aarch64 SVE dwarf regnums

Alan Hayward
2018-06-06T15:17:14Z

Simply add the Dwarf VG register checks.

This is as per the spec:
https://developer.arm.com/products/architecture/a-profile/docs/100985/0000

2018-06-06 Alan Hayward <alan.hayward@arm.com>

* aarch64-tdep.c (aarch64_dwarf_reg_to_regnum): Add mappings.
* aarch64-tdep.h (AARCH64_DWARF_SVE_VG): Add define.
(AARCH64_DWARF_SVE_FFR): Likewise.
(AARCH64_DWARF_SVE_P0): Likewise.
(AARCH64_DWARF_SVE_Z0): Likewise.
---
gdb/aarch64-tdep.c | 13 ++++++++++++-
gdb/aarch64-tdep.h | 4 ++++
2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 0438ab83cd..cfe22213cd 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -1806,9 +1806,20 @@ aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;

+ if (reg == AARCH64_DWARF_SVE_VG)
+ return AARCH64_SVE_VG_REGNUM;
+
+ if (reg == AARCH64_DWARF_SVE_FFR)
+ return AARCH64_SVE_FFR_REGNUM;
+
+ if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
+ return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
+
+ if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
+ return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
+
return -1;
}
-\f

/* Implement the "print_insn" gdbarch method. */

diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 5a319551e6..7e5031f0fd 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -32,6 +32,10 @@ struct regset;
#define AARCH64_DWARF_X0 0
#define AARCH64_DWARF_SP 31
#define AARCH64_DWARF_V0 64
+#define AARCH64_DWARF_SVE_VG 46
+#define AARCH64_DWARF_SVE_FFR 47
+#define AARCH64_DWARF_SVE_P0 48
+#define AARCH64_DWARF_SVE_Z0 96

/* Size of integer registers. */
#define X_REGISTER_SIZE 8
--
2.15.1 (Apple Git-101)