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Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A797.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6652 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org --_000_AS8PR08MB10099E7285C79E152E1D56E8D9BC02AS8PR08MB10099eu_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable >> * p/x $por_el0 >> * set $por_el0 =3D >> >> Example: >> (gdb) info register por_el0 >> por_el0 0x7 [ P15=3D--- P14=3D--- P13=3D--- P12= =3D--- P11=3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4= =3D--- P3=3D--- P2=3D--- P1=3D--- P0=3Drwx ] >> (gdb) set $por_el0=3D0xffffffff77777777 >> (gdb) info register por_el0 >> por_el0 0xffffffff77777777 [ P15=3D??? P14=3D??? P13=3D??? P12= =3D??? P11=3D??? P10=3D??? P9=3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4= =3Drwx P3=3Drwx P2=3Drwx P1=3Drwx P0=3Drwx ] >> (gdb) p $por_el0 >> $1 =3D [ P15=3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D??? P9= =3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx P1=3D= rwx P0=3Drwx ] >> (gdb) p/x $por_el0 >> $2 =3D 0xffffffff77777777 >> (gdb) set $por_el0=3D0x57 >> (gdb) info register por_el0 >> por_el0 0x57 [ P15=3D--- P14=3D--- P13=3D--- P12= =3D--- P11=3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4= =3D--- P3=3D--- P2=3D--- P1=3Drw- P0=3Drwx ] >> (gdb) set $por_el0=3D0xf7f7f7f7f7f7f7f7 >> (gdb) info register por_el0 >> por_el0 0xf7f7f7f7f7f7f7f7 [ P15=3D??? P14=3Drwx P13=3D??? P12= =3Drwx P11=3D??? P10=3Drwx P9=3D??? P8=3Drwx P7=3D??? P6=3Drwx P5=3D??? P4= =3Drwx P3=3D??? P2=3Drwx P1=3D??? P0=3Drwx ] >> (gdb) > >Looking at the output above I think it is a bit hard to read. > >Have you considered keeping the original register as it is and having >pseudo-registers that print appropriately? > >If a user wants to see, say, P15, it doesn=B4t help we print everything >else along with it. > >The other alternative is having a python pretty printer that goes >alongside the feature. > Hi Luis, Thanks for the suggestions. The reason I chose to decode the register inline is that the raw 64 bit reg= ister value by itself is not particularly useful. For example, if we kept the ori= ginal formatting, the user would see something like: (gdb) set $por_el0 =3D 0xf7f7f7f7f7f7f7f7 (gdb) info register por_el0 por_el0 0xf7f7f7f7f7f7f7f7 17868022691004925943 Neither of hexadecimal nor the decimal value tells the user which protectio= n key has which permissions without manually decoding each 4-bit nibble. Although the architecture defines POR_EL0 as a single 64 bit register, it doesn't define separate P0-P15 fields. I introduced the P0-P15 labels to identify each 4-bit nibble, since each nibble corresponds to one protect= ion key's permission encoding. We also considered only displaying nibbles that have at least one permissio= n enabled, while displaying "???" when the reserved fourth bit of a nibble is= set. For example: (gdb) set $por_el0 =3D 0x57 (gdb) info register por_el0 por_el0 0x57 [ P1=3Drw- P0=3Drwx ] (gdb) set $por_el0 =3D 0xf7 (gdb) info register por_el0 por_el0 0xf7 [ P1=3D??? P0=3Drwx ] However, we thought that approach could be misleading because it hides the remaining protection keys rather than explicitly showing that they are all "---", please let me know if you feel this approach is better? Regarding the Python pretty-printer suggestion, could you elaborate a bit o= n what you have in mind? Would you prefer the Python pretty printer to displa= y the same string format, or a shorter form that still allows accessing each nibb= le individually (e.g., P0, P5, etc.)? Also, could you provide a simple example= of the expected output? Thanks, Sri. ________________________________ From: Luis Sent: 21 July 2026 21:25 To: Srinath Parvathaneni ; gdb-patches@source= ware.org Cc: guinevere@redhat.com ; thiago.bauermann@linaro.or= g ; Ezra Sitorus ; Matth= ieu Longo ; simark@simark.ca Subject: Re: [PATCH v3 1/5] [PATCH 1/5] gdb/aarch64: Add POR_EL0 register s= upport for FEAT_S1POE Sorry, missed some... On 14/07/2026 21:15, srinath.parvathaneni@arm.com wrote: > From: Srinath Parvathaneni > > Add support for the FEAT_S1POE POR_EL0 register on AArch64. > > This patch adds POR_EL0 to the AArch64 register set and reads/writes it > using the NT_ARM_POE ptrace regset. > > With this change, POR_EL0 is available through: > * info registers > * info registers por_el0 > * p $por_el0 > * p/x $por_el0 > * set $por_el0 =3D > > Example: > (gdb) info register por_el0 > por_el0 0x7 [ P15=3D--- P14=3D--- P13=3D--- P12=3D= --- P11=3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D-= -- P3=3D--- P2=3D--- P1=3D--- P0=3Drwx ] > (gdb) set $por_el0=3D0xffffffff77777777 > (gdb) info register por_el0 > por_el0 0xffffffff77777777 [ P15=3D??? P14=3D??? P13=3D??? P12=3D= ??? P11=3D??? P10=3D??? P9=3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Dr= wx P3=3Drwx P2=3Drwx P1=3Drwx P0=3Drwx ] > (gdb) p $por_el0 > $1 =3D [ P15=3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D??? P9= =3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx P1=3D= rwx P0=3Drwx ] > (gdb) p/x $por_el0 > $2 =3D 0xffffffff77777777 > (gdb) set $por_el0=3D0x57 > (gdb) info register por_el0 > por_el0 0x57 [ P15=3D--- P14=3D--- P13=3D--- P12=3D= --- P11=3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D-= -- P3=3D--- P2=3D--- P1=3Drw- P0=3Drwx ] > (gdb) set $por_el0=3D0xf7f7f7f7f7f7f7f7 > (gdb) info register por_el0 > por_el0 0xf7f7f7f7f7f7f7f7 [ P15=3D??? P14=3Drwx P13=3D??? P12=3D= rwx P11=3D??? P10=3Drwx P9=3D??? P8=3Drwx P7=3D??? P6=3Drwx P5=3D??? P4=3Dr= wx P3=3D??? P2=3Drwx P1=3D??? P0=3Drwx ] > (gdb) > --- > gdb/Makefile.in | 2 ++ > gdb/aarch64-linux-nat.c | 64 +++++++++++++++++++++++++++++++++ > gdb/aarch64-tdep.c | 23 ++++++++++++ > gdb/aarch64-tdep.h | 10 ++++++ > gdb/arch/aarch64-poe-linux.h | 29 +++++++++++++++ > gdb/arch/aarch64.c | 4 +++ > gdb/arch/aarch64.h | 8 ++++- > gdb/features/Makefile | 1 + > gdb/features/aarch64-poe.c | 68 ++++++++++++++++++++++++++++++++++++ > gdb/features/aarch64-poe.xml | 47 +++++++++++++++++++++++++ > gdb/nat/aarch64-poe-linux.h | 29 +++++++++++++++ > 11 files changed, 284 insertions(+), 1 deletion(-) > create mode 100644 gdb/arch/aarch64-poe-linux.h > create mode 100644 gdb/features/aarch64-poe.c > create mode 100644 gdb/features/aarch64-poe.xml > create mode 100644 gdb/nat/aarch64-poe-linux.h > > diff --git a/gdb/Makefile.in b/gdb/Makefile.in > index 57f384170ab..3dc9cd07dcb 100644 > --- a/gdb/Makefile.in > +++ b/gdb/Makefile.in > @@ -1292,6 +1292,7 @@ HFILES_NO_SRCDIR =3D \ > arch/aarch32.h \ > arch/aarch64-fpmr-linux.h \ > arch/aarch64-gcs-linux.h \ > + arch/aarch64-poe-linux.h \ > arch/aarch64.h \ > arch/aarch64-insn.h \ > arch/aarch64-mte.h \ > @@ -1540,6 +1541,7 @@ HFILES_NO_SRCDIR =3D \ > namespace.h \ > nat/aarch64-fpmr-linux.h \ > nat/aarch64-gcs-linux.h \ > + nat/aarch64-poe-linux.h \ > nat/aarch64-hw-point.h \ > nat/aarch64-linux.h \ > nat/aarch64-linux-hw-point.h \ Let's keep these entries sorted alphabetically. > diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c > index 52ace4aab41..8e29c42908c 100644 > --- a/gdb/aarch64-linux-nat.c > +++ b/gdb/aarch64-linux-nat.c > @@ -34,6 +34,7 @@ > #include "arch/arm.h" > #include "nat/aarch64-fpmr-linux.h" > #include "nat/aarch64-gcs-linux.h" > +#include "nat/aarch64-poe-linux.h" > #include "nat/aarch64-linux.h" > #include "nat/aarch64-linux-hw-point.h" > #include "nat/aarch64-mte-linux-ptrace.h" > @@ -602,6 +603,54 @@ store_gcsregs_to_thread (regcache *regcache) > perror_with_name (_("Unable to store GCS registers")); > } > > +/* Fill GDB's register array with the POE register value from the curren= t > + thread. */ > + > +static void > +fetch_poeregs_from_thread (regcache *regcache) > +{ > + aarch64_gdbarch_tdep *tdep > + =3D gdbarch_tdep (regcache->arch ()); > + > + gdb_assert (tdep->has_poe ()); > + > + uint64_t user_poe; > + iovec iovec; > + > + iovec.iov_base =3D &user_poe; > + iovec.iov_len =3D sizeof (user_poe); > + > + int tid =3D get_ptrace_pid (regcache->ptid ()); > + if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_POE, &iovec) !=3D 0) > + perror_with_name (_("Unable to fetch POE register")); > + > + regcache->raw_supply (tdep->poe_regnum, &user_poe); > +} > + > +/* Store the NT_ARM_POE register contents from GDB's REGCACHE to the > + thread associated with REGCACHE. */ wront identation above. > + > +static void > +store_poeregs_to_thread (struct regcache *regcache) > +{ > + aarch64_gdbarch_tdep *tdep > + =3D gdbarch_tdep (regcache->arch ()); > + > + gdb_assert (tdep->has_poe ()); > + > + int tid =3D regcache->ptid ().lwp (); > + > + iovec iovec; > + uint64_t user_poe; > + iovec.iov_base =3D &user_poe; > + iovec.iov_len =3D sizeof (user_poe); > + > + regcache->raw_collect (tdep->poe_regnum, &user_poe); > + > + if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_POE, &iovec) !=3D 0) > + perror_with_name (_("Unable to store POE register")); > +} > + > /* Fill GDB's REGCACHE with the FPMR register set content from the > thread associated with REGCACHE. */ > > @@ -683,6 +732,9 @@ aarch64_fetch_registers (struct regcache *regcache, i= nt regno) > if (tdep->has_gcs_linux ()) > fetch_gcsregs_from_thread (regcache); > > + if (tdep->has_poe ()) > + fetch_poeregs_from_thread (regcache); > + > if (tdep->has_fpmr ()) > fetch_fpmr_from_thread (regcache); > } > @@ -722,6 +774,9 @@ aarch64_fetch_registers (struct regcache *regcache, i= nt regno) > && (regno =3D=3D tdep->gcs_reg_base || regno =3D=3D tdep->gcs_l= inux_reg_base > || regno =3D=3D tdep->gcs_linux_reg_base + 1)) > fetch_gcsregs_from_thread (regcache); > + /* POE register? */ > + else if (tdep->has_poe () && (regno =3D=3D tdep->poe_regnum)) > + fetch_poeregs_from_thread (regcache); > /* FPMR? */ > else if (tdep->has_fpmr () && (regno =3D=3D tdep->fpmr_regnum)) > fetch_fpmr_from_thread (regcache); > @@ -802,6 +857,9 @@ aarch64_store_registers (struct regcache *regcache, i= nt regno) > > if (tdep->has_fpmr ()) > store_fpmr_to_thread (regcache); > + > + if (tdep->has_poe ()) > + store_poeregs_to_thread (regcache); > } > /* General purpose register? */ > else if (regno < AARCH64_V0_REGNUM) > @@ -836,6 +894,9 @@ aarch64_store_registers (struct regcache *regcache, i= nt regno) > /* FPMR? */ > else if (tdep->has_fpmr () && regno =3D=3D tdep->fpmr_regnum) > store_fpmr_to_thread (regcache); > + /* POE register? */ > + else if (tdep->has_poe () && regno =3D=3D tdep->poe_regnum) > + store_poeregs_to_thread (regcache); > > /* PAuth registers are read-only. */ > } > @@ -1024,6 +1085,9 @@ aarch64_linux_nat_target::read_description () > /* Check for FPMR. */ > features.fpmr =3D hwcap2 & HWCAP2_FPMR; > > + /* Check for POE support. */ > + features.poe =3D hwcap2 & HWCAP2_POE; > + > return aarch64_read_description (features); > } > > diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c > index a84da1fd59e..2e86d6e0452 100644 > --- a/gdb/aarch64-tdep.c > +++ b/gdb/aarch64-tdep.c > @@ -164,6 +164,11 @@ static const char *const aarch64_gcs_register_names[= ] =3D { > "gcspr" > }; > > +static const char *const aarch64_poe_register_names[] =3D { > + /* Permission Overlay Extension Register. */ > + "por_el0" > +}; > + > static const char *const aarch64_gcs_linux_register_names[] =3D { > /* Field in struct user_gcs. */ > "gcs_features_enabled", > @@ -4136,6 +4141,10 @@ aarch64_features_from_target_desc (const struct ta= rget_desc *tdesc) > features.fpmr =3D (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fp= mr") > !=3D nullptr); > > + /* Check for POE feature. */ > + features.poe =3D (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.poe"= ) > + !=3D nullptr); > + > return features; > } > > @@ -4556,6 +4565,19 @@ aarch64_gdbarch_init (struct gdbarch_info info, st= ruct gdbarch_list *arches) > fpmr_regnum, "fpmr"); > } > > + int poe_regnum =3D -1; > + const struct tdesc_feature *feature_poe > + =3D tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.poe"); > + if (feature_poe !=3D nullptr) > + { > + poe_regnum =3D num_regs; > + for (i =3D 0; i < ARRAY_SIZE (aarch64_poe_register_names); i++) > + valid_p &=3D tdesc_numbered_register (feature_poe, tdesc_data.get (= ), > + poe_regnum + i, > + aarch64_poe_register_names[i]); > + num_regs++; > + } > + > int first_sme_regnum =3D -1; > int first_sme2_regnum =3D -1; > int first_sme_pseudo_regnum =3D -1; > @@ -4756,6 +4778,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, str= uct gdbarch_list *arches) > tdep->gcs_reg_base =3D first_gcs_regnum; > tdep->gcs_linux_reg_base =3D first_gcs_linux_regnum; > tdep->fpmr_regnum =3D fpmr_regnum; > + tdep->poe_regnum =3D poe_regnum; > > /* Set the SME register set details. The pseudo-registers will be ad= justed > later. */ > diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h > index dff05a08f84..3c5d10beee5 100644 > --- a/gdb/aarch64-tdep.h > +++ b/gdb/aarch64-tdep.h > @@ -208,6 +208,16 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base > return gcs_linux_reg_base !=3D -1; > } > > + /* POE register. This is -1 if no POE feature is available. */ > + int poe_regnum =3D -1; > + > + /* Returns true if the target supports the POE feature. */ > + bool > + has_poe () const > + { > + return poe_regnum !=3D -1; > + } > + > /* First FPMR register. This is -1 if FPMR is not supported. */ > int fpmr_regnum =3D -1; > > diff --git a/gdb/arch/aarch64-poe-linux.h b/gdb/arch/aarch64-poe-linux.h > new file mode 100644 > index 00000000000..8623fa43b54 > --- /dev/null > +++ b/gdb/arch/aarch64-poe-linux.h > @@ -0,0 +1,29 @@ > +/* Common Linux target-dependent definitions for AArch64 POE > + > + Copyright (C) 2026 Free Software Foundation, Inc. > + > + This file is part of GDB. > + > + This program is free software; you can redistribute it and/or modify > + it under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + This program is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with this program. If not, see .= */ > + > +#ifndef GDB_ARCH_AARCH64_POE_LINUX_H > +#define GDB_ARCH_AARCH64_POE_LINUX_H > + > +/* Feature check for Permission Overlay Extension. */ > +#define AARCH64_HWCAP2_POE (1ULL << 63) > + > +/* Data or instruction abort caused by Protection Key Violation. */ > +#define AARCH64_SEGV_PKUERR 4 > + > +#endif /* GDB_ARCH_AARCH64_POE_LINUX_H. */ > diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c > index 2401a325b7b..a567938d06d 100644 > --- a/gdb/arch/aarch64.c > +++ b/gdb/arch/aarch64.c > @@ -28,6 +28,7 @@ > #include "../features/aarch64-sme2.c" > #include "../features/aarch64-tls.c" > #include "../features/aarch64-gcs.c" > +#include "../features/aarch64-poe.c" > #include "../features/aarch64-gcs-linux.c" > > /* See arch/aarch64.h. */ > @@ -77,6 +78,9 @@ aarch64_create_target_description (const aarch64_featur= es &features) > if (features.fpmr) > regnum =3D create_feature_aarch64_fpmr (tdesc.get (), regnum); > > + if (features.poe) > + regnum =3D create_feature_aarch64_poe (tdesc.get (), regnum); > + > return tdesc; > } > > diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h > index cf7318cbe74..ba90d55c3bb 100644 > --- a/gdb/arch/aarch64.h > +++ b/gdb/arch/aarch64.h > @@ -35,6 +35,8 @@ struct aarch64_features > bool pauth =3D false; > bool mte =3D false; > bool fpmr =3D false; > + /* Whether the Permission Overlay Extension (FEAT_S1POE) is supported.= */ > + bool poe =3D false; > > /* A positive TLS value indicates the number of TLS registers availab= le. */ > uint8_t tls =3D 0; > @@ -70,7 +72,8 @@ inline bool operator=3D=3D(const aarch64_features &lhs,= const aarch64_features &rhs) > && lhs.sme2 =3D=3D rhs.sme2 > && lhs.gcs =3D=3D rhs.gcs > && lhs.gcs_linux =3D=3D rhs.gcs_linux > - && lhs.fpmr =3D=3D rhs.fpmr; > + && lhs.fpmr =3D=3D rhs.fpmr > + && lhs.poe =3D=3D rhs.poe; > } > > namespace std > @@ -103,6 +106,9 @@ namespace std > > /* FPMR feature. */ > h =3D h << 1 | features.fpmr; > + > + /* POE feature. */ > + h =3D h << 1 | features.poe; > return h; > } > }; > diff --git a/gdb/features/Makefile b/gdb/features/Makefile > index 161a7453d66..cc77e5bb652 100644 > --- a/gdb/features/Makefile > +++ b/gdb/features/Makefile > @@ -207,6 +207,7 @@ FEATURE_XMLFILES =3D aarch64-core.xml \ > aarch64-pauth.xml \ > aarch64-mte.xml \ > aarch64-gcs.xml \ > + aarch64-poe.xml \ > aarch64-gcs-linux.xml \ > arc/v1-core.xml \ > arc/v1-aux.xml \ > diff --git a/gdb/features/aarch64-poe.c b/gdb/features/aarch64-poe.c > new file mode 100644 > index 00000000000..4bd795e9fe6 > --- /dev/null > +++ b/gdb/features/aarch64-poe.c > @@ -0,0 +1,68 @@ > +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: > + Original: aarch64-poe.xml */ > + > +#include "gdbsupport/tdesc.h" > + > +static int > +create_feature_aarch64_poe (struct target_desc *result, long regnum) > +{ > + struct tdesc_feature *feature; > + > + feature =3D tdesc_create_feature (result, "org.gnu.gdb.aarch64.poe"); > + tdesc_type_with_fields *type_with_fields; > + type_with_fields =3D tdesc_create_enum (feature, "por_el0_fmt", 4); > + tdesc_add_enum_value (type_with_fields, 0, "---"); > + tdesc_add_enum_value (type_with_fields, 1, "r--"); > + tdesc_add_enum_value (type_with_fields, 2, "--x"); > + tdesc_add_enum_value (type_with_fields, 3, "r-x"); > + tdesc_add_enum_value (type_with_fields, 4, "-w-"); > + tdesc_add_enum_value (type_with_fields, 5, "rw-"); > + tdesc_add_enum_value (type_with_fields, 6, "-wx"); > + tdesc_add_enum_value (type_with_fields, 7, "rwx"); > + tdesc_add_enum_value (type_with_fields, 8, "???"); > + tdesc_add_enum_value (type_with_fields, 9, "???"); > + tdesc_add_enum_value (type_with_fields, 10, "???"); > + tdesc_add_enum_value (type_with_fields, 11, "???"); > + tdesc_add_enum_value (type_with_fields, 12, "???"); > + tdesc_add_enum_value (type_with_fields, 13, "???"); > + tdesc_add_enum_value (type_with_fields, 14, "???"); > + tdesc_add_enum_value (type_with_fields, 15, "???"); > + > + type_with_fields =3D tdesc_create_flags (feature, "por_el0_flags", 8); > + tdesc_type *field_type; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P15", 60, 63, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P14", 56, 59, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P13", 52, 55, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P12", 48, 51, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P11", 44, 47, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P10", 40, 43, field_type)= ; > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P9", 36, 39, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P8", 32, 35, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P7", 28, 31, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P6", 24, 27, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P5", 20, 23, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P4", 16, 19, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P3", 12, 15, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P2", 8, 11, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P1", 4, 7, field_type); > + field_type =3D tdesc_named_type (feature, "por_el0_fmt"); > + tdesc_add_typed_bitfield (type_with_fields, "P0", 0, 3, field_type); > + > + tdesc_create_reg (feature, "por_el0", regnum++, 1, "system", 64, "por_= el0_flags"); > + return regnum; > +} > diff --git a/gdb/features/aarch64-poe.xml b/gdb/features/aarch64-poe.xml > new file mode 100644 > index 00000000000..58fc4f80d5c > --- /dev/null > +++ b/gdb/features/aarch64-poe.xml > @@ -0,0 +1,47 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb/nat/aarch64-poe-linux.h b/gdb/nat/aarch64-poe-linux.h > new file mode 100644 > index 00000000000..f3d0256da3f > --- /dev/null > +++ b/gdb/nat/aarch64-poe-linux.h > @@ -0,0 +1,29 @@ > +/* Common native Linux definitions for AArch64 Permission Overlay Extens= ion. > + > + Copyright (C) 2026 Free Software Foundation, Inc. > + > + This file is part of GDB. > + > + This program is free software; you can redistribute it and/or modify > + it under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + This program is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with this program. If not, see .= */ > + > +#include Shouldn=B4t the above be inside the include guard? > +#ifndef GDB_NAT_AARCH64_POE_LINUX_H > +#define GDB_NAT_AARCH64_POE_LINUX_H > + > +/* Feature check for Permission Overlay Extension. */ > +#ifndef HWCAP2_POE > +#define HWCAP2_POE (1ULL << 63) > +#endif /* HWCAP2_POE. */ > + > +#endif /* GDB_NAT_AARCH64_POE_LINUX_H. */ --_000_AS8PR08MB10099E7285C79E152E1D56E8D9BC02AS8PR08MB10099eu_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
>> *  p/x $por_el0
>> *  set $por_el0 =3D <value>
>> 
>> Example:
>> (gdb) info register por_el0
>> por_el0        0x7        =         [ P15=3D--- P14=3D--- P13=3D--- P12=3D--- P11= =3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D--- P3= =3D--- P2=3D--- P1=3D--- P0=3Drwx ]
>> (gdb) set $por_el0=3D0xffffffff77777777
>> (gdb) info register por_el0
>> por_el0        0xffffffff77777777  [ P15= =3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D??? P9=3D??? P8=3D??? = P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx P1=3Drwx P0=3Drwx ]
>> (gdb) p $por_el0
>> $1 =3D [ P15=3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D?= ?? P9=3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx = P1=3Drwx P0=3Drwx ]
>> (gdb) p/x $por_el0
>> $2 =3D 0xffffffff77777777
>> (gdb) set $por_el0=3D0x57
>> (gdb) info register por_el0
>> por_el0        0x57        = ;        [ P15=3D--- P14=3D--- P13=3D--- P12=3D--- P11= =3D--- P10=3D--- P9=3D--- P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D--- P3= =3D--- P2=3D--- P1=3Drw- P0=3Drwx ]
>> (gdb) set $por_el0=3D0xf7f7f7f7f7f7f7f7
>> (gdb) info register por_el0
>> por_el0        0xf7f7f7f7f7f7f7f7  [ P15= =3D??? P14=3Drwx P13=3D??? P12=3Drwx P11=3D??? P10=3Drwx P9=3D??? P8=3Drwx = P7=3D??? P6=3Drwx P5=3D??? P4=3Drwx P3=3D??? P2=3Drwx P1=3D??? P0=3Drwx ]
>> (gdb)
>
>Looking at the output above I think it is a bit hard to read.
>
>Have you considered keeping the original register as it is and having&n= bsp;
>pseudo-registers that print appropriately?
>
>If a user wants to see, say, P15, it doesn=B4t help we print everything=  
>else along with it.
>
>The other alternative is having a python pretty printer that goes =
>alongside the feature.
>

Hi Luis,

Thanks for the suggestions.

The reason I chose to decode the register inline is that the raw 64 bit reg= ister
value by itself is not particularly useful. For example, if we kept the ori= ginal
formatting, the user would see something like:

(gdb) set $por_el0 =3D 0xf7f7f7f7f7f7f7f7
(gdb) info register por_el0
por_el0         0xf7f7f7f7f7f7f7f7      = 17868022691004925943

Neither of hexadecimal nor the decimal value tells the user which protectio= n key
has which permissions without manually decoding each 4-bit nibble.

Although the architecture defines POR_EL0 as a single 64 bit register, it
doesn't define separate P0-P15 fields. I introduced the P0-P15 labels
to identify each 4-bit nibble, since each nibble corresponds to one protect= ion
key's permission encoding.

We also considered only displaying nibbles that have at least one permissio= n
enabled, while displaying "???" when the reserved fourth bit of a= nibble is set.
For example:

(gdb) set $por_el0 =3D 0x57
(gdb) info register por_el0
por_el0        0x57  [ P1=3Drw- P0=3Drwx ]

(gdb) set $por_el0 =3D 0xf7
(gdb) info register por_el0
por_el0        0xf7  [ P1=3D??? P0=3Drwx ]

However, we thought that approach could be misleading because it hides the<= /div>
remaining protection keys rather than explicitly showing that they are all<= /div>
"---", please let me know if you feel this approach is better?

Regarding the Python pretty-printer suggestion, could you elaborate a bit o= n
what you have in mind? Would you prefer the Python pretty printer to displa= y the
same string format, or a shorter form that still allows accessing each nibb= le
individually (e.g., P0, P5, etc.)? Also, could you provide a simple example= of
the expected output?

Thanks,
Sri.
From: Luis <luis.machado= .foss@gmail.com>
Sent: 21 July 2026 21:25
To: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>; gdb-p= atches@sourceware.org <gdb-patches@sourceware.org>
Cc: guinevere@redhat.com <guinevere@redhat.com>; thiago.bauerm= ann@linaro.org <thiago.bauermann@linaro.org>; Ezra Sitorus <Ezra.S= itorus@arm.com>; Matthieu Longo <Matthieu.Longo@arm.com>; simark@s= imark.ca <simark@simark.ca>
Subject: Re: [PATCH v3 1/5] [PATCH 1/5] gdb/aarch64: Add POR_EL0 reg= ister support for FEAT_S1POE
 
Sorry, missed some...

On 14/07/2026 21:15, srinath.parvathaneni@arm.com wrote:
> From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
>
> Add support for the FEAT_S1POE POR_EL0 register on AArch64.
>
> This patch adds POR_EL0 to the AArch64 register set and reads/writes i= t
> using the NT_ARM_POE ptrace regset.
>
> With this change, POR_EL0 is available through:
> *  info registers
> *  info registers por_el0
> *  p $por_el0
> *  p/x $por_el0
> *  set $por_el0 =3D <value>
>
> Example:
> (gdb) info register por_el0
> por_el0        0x7   = ;            &n= bsp; [ P15=3D--- P14=3D--- P13=3D--- P12=3D--- P11=3D--- P10=3D--- P9=3D---= P8=3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D--- P3=3D--- P2=3D--- P1=3D--- P0= =3Drwx ]
> (gdb) set $por_el0=3D0xffffffff77777777
> (gdb) info register por_el0
> por_el0        0xffffffff77777777&n= bsp; [ P15=3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D??? P9=3D???= P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx P1=3Drwx P0= =3Drwx ]
> (gdb) p $por_el0
> $1 =3D [ P15=3D??? P14=3D??? P13=3D??? P12=3D??? P11=3D??? P10=3D??? P= 9=3D??? P8=3D??? P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx P3=3Drwx P2=3Drwx P1= =3Drwx P0=3Drwx ]
> (gdb) p/x $por_el0
> $2 =3D 0xffffffff77777777
> (gdb) set $por_el0=3D0x57
> (gdb) info register por_el0
> por_el0        0x57  &nbs= p;             = [ P15=3D--- P14=3D--- P13=3D--- P12=3D--- P11=3D--- P10=3D--- P9=3D--- P8= =3D--- P7=3D--- P6=3D--- P5=3D--- P4=3D--- P3=3D--- P2=3D--- P1=3Drw- P0=3D= rwx ]
> (gdb) set $por_el0=3D0xf7f7f7f7f7f7f7f7
> (gdb) info register por_el0
> por_el0        0xf7f7f7f7f7f7f7f7&n= bsp; [ P15=3D??? P14=3Drwx P13=3D??? P12=3Drwx P11=3D??? P10=3Drwx P9=3D???= P8=3Drwx P7=3D??? P6=3Drwx P5=3D??? P4=3Drwx P3=3D??? P2=3Drwx P1=3D??? P0= =3Drwx ]
> (gdb)
> ---
>   gdb/Makefile.in       &= nbsp;      |  2 ++
>   gdb/aarch64-linux-nat.c      | 64= +++++++++++++++++++++++++++++++++
>   gdb/aarch64-tdep.c      &nbs= p;    | 23 ++++++++++++
>   gdb/aarch64-tdep.h      &nbs= p;    | 10 ++++++
>   gdb/arch/aarch64-poe-linux.h | 29 +++++++++++++++
>   gdb/arch/aarch64.c      &nbs= p;    |  4 +++
>   gdb/arch/aarch64.h      &nbs= p;    |  8 ++++-
>   gdb/features/Makefile      &= nbsp; |  1 +
>   gdb/features/aarch64-poe.c   | 68 ++++++++++++++= ++++++++++++++++++++++
>   gdb/features/aarch64-poe.xml | 47 ++++++++++++++++++++++++= +
>   gdb/nat/aarch64-poe-linux.h  | 29 +++++++++++++++
>   11 files changed, 284 insertions(+), 1 deletion(-)
>   create mode 100644 gdb/arch/aarch64-poe-linux.h
>   create mode 100644 gdb/features/aarch64-poe.c
>   create mode 100644 gdb/features/aarch64-poe.xml
>   create mode 100644 gdb/nat/aarch64-poe-linux.h
>
> diff --git a/gdb/Makefile.in b/gdb/Makefile.in
> index 57f384170ab..3dc9cd07dcb 100644
> --- a/gdb/Makefile.in
> +++ b/gdb/Makefile.in
> @@ -1292,6 +1292,7 @@ HFILES_NO_SRCDIR =3D \
>        arch/aarch32.h \
>        arch/aarch64-fpmr-linux.h \<= br> >        arch/aarch64-gcs-linux.h \ > +     arch/aarch64-poe-linux.h \
>        arch/aarch64.h \
>        arch/aarch64-insn.h \
>        arch/aarch64-mte.h \
> @@ -1540,6 +1541,7 @@ HFILES_NO_SRCDIR =3D \
>        namespace.h \
>        nat/aarch64-fpmr-linux.h \ >        nat/aarch64-gcs-linux.h \ > +     nat/aarch64-poe-linux.h \
>        nat/aarch64-hw-point.h \
>        nat/aarch64-linux.h \
>        nat/aarch64-linux-hw-point.h= \

Let's keep these entries sorted alphabetically.

> diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
> index 52ace4aab41..8e29c42908c 100644
> --- a/gdb/aarch64-linux-nat.c
> +++ b/gdb/aarch64-linux-nat.c
> @@ -34,6 +34,7 @@
>   #include "arch/arm.h"
>   #include "nat/aarch64-fpmr-linux.h"
>   #include "nat/aarch64-gcs-linux.h"
> +#include "nat/aarch64-poe-linux.h"
>   #include "nat/aarch64-linux.h"
>   #include "nat/aarch64-linux-hw-point.h"
>   #include "nat/aarch64-mte-linux-ptrace.h"
> @@ -602,6 +603,54 @@ store_gcsregs_to_thread (regcache *regcache)
>       perror_with_name (_("Unable t= o store GCS registers"));
>   }
>  
> +/* Fill GDB's register array with the POE register value from the cur= rent
> +   thread.  */
> +
> +static void
> +fetch_poeregs_from_thread (regcache *regcache)
> +{
> +  aarch64_gdbarch_tdep *tdep
> +    =3D gdbarch_tdep<aarch64_gdbarch_tdep> (regc= ache->arch ());
> +
> +  gdb_assert (tdep->has_poe ());
> +
> +  uint64_t user_poe;
> +  iovec iovec;
> +
> +  iovec.iov_base =3D &user_poe;
> +  iovec.iov_len =3D sizeof (user_poe);
> +
> +  int tid =3D get_ptrace_pid (regcache->ptid ());
> +  if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_POE, &iovec) != =3D 0)
> +    perror_with_name (_("Unable to fetch POE regi= ster"));
> +
> +  regcache->raw_supply (tdep->poe_regnum, &user_poe);<= br> > +}
> +
> +/* Store the NT_ARM_POE register contents from GDB's REGCACHE to the<= br> > +    thread associated with REGCACHE.  */

wront identation above.

> +
> +static void
> +store_poeregs_to_thread (struct regcache *regcache)
> +{
> +  aarch64_gdbarch_tdep *tdep
> +    =3D gdbarch_tdep<aarch64_gdbarch_tdep> (regc= ache->arch ());
> +
> +  gdb_assert (tdep->has_poe ());
> +
> +  int tid =3D regcache->ptid ().lwp ();
> +
> +  iovec iovec;
> +  uint64_t user_poe;
> +  iovec.iov_base =3D &user_poe;
> +  iovec.iov_len =3D sizeof (user_poe);
> +
> +  regcache->raw_collect (tdep->poe_regnum, &user_poe);=
> +
> +  if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_POE, &iovec) != =3D 0)
> +    perror_with_name (_("Unable to store POE regi= ster"));
> +}
> +
>   /* Fill GDB's REGCACHE with the FPMR register set content = from the
>      thread associated with REGCACHE.  *= /
>  
> @@ -683,6 +732,9 @@ aarch64_fetch_registers (struct regcache *regcache= , int regno)
>         if (tdep->has_gcs_l= inux ())
>        fetch_gcsregs_from_thread (r= egcache);
>  
> +      if (tdep->has_poe ())
> +     fetch_poeregs_from_thread (regcache);
> +
>         if (tdep->has_fpmr = ())
>        fetch_fpmr_from_thread (regc= ache);
>       }
> @@ -722,6 +774,9 @@ aarch64_fetch_registers (struct regcache *regcache= , int regno)
>           &&= (regno =3D=3D tdep->gcs_reg_base || regno =3D=3D tdep->gcs_linux_reg= _base
>            = ;   || regno =3D=3D tdep->gcs_linux_reg_base + 1))
>       fetch_gcsregs_from_thread (regcach= e);
> +  /* POE register?  */
> +  else if (tdep->has_poe () && (regno =3D=3D tdep->= ;poe_regnum))
> +    fetch_poeregs_from_thread (regcache);
>     /* FPMR?  */
>     else if (tdep->has_fpmr () && (regn= o =3D=3D tdep->fpmr_regnum))
>       fetch_fpmr_from_thread (regcache);=
> @@ -802,6 +857,9 @@ aarch64_store_registers (struct regcache *regcache= , int regno)
>  
>         if (tdep->has_fpmr = ())
>        store_fpmr_to_thread (regcac= he);
> +
> +      if (tdep->has_poe ())
> +     store_poeregs_to_thread (regcache);
>       }
>     /* General purpose register?  */
>     else if (regno < AARCH64_V0_REGNUM)
> @@ -836,6 +894,9 @@ aarch64_store_registers (struct regcache *regcache= , int regno)
>     /* FPMR?  */
>     else if (tdep->has_fpmr () && regno= =3D=3D tdep->fpmr_regnum)
>       store_fpmr_to_thread (regcache); > +  /* POE register?  */
> +  else if (tdep->has_poe () && regno =3D=3D tdep->= poe_regnum)
> +    store_poeregs_to_thread (regcache);
>  
>     /* PAuth registers are read-only.  */
>   }
> @@ -1024,6 +1085,9 @@ aarch64_linux_nat_target::read_description () >     /* Check for FPMR.  */
>     features.fpmr =3D hwcap2 & HWCAP2_FPMR; >  
> +  /* Check for POE support.  */
> +  features.poe =3D hwcap2 & HWCAP2_POE;
> +
>     return aarch64_read_description (features); >   }
>  
> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
> index a84da1fd59e..2e86d6e0452 100644
> --- a/gdb/aarch64-tdep.c
> +++ b/gdb/aarch64-tdep.c
> @@ -164,6 +164,11 @@ static const char *const aarch64_gcs_register_nam= es[] =3D {
>     "gcspr"
>   };
>  
> +static const char *const aarch64_poe_register_names[] =3D {
> +  /* Permission Overlay Extension Register.  */
> +  "por_el0"
> +};
> +
>   static const char *const aarch64_gcs_linux_register_names[= ] =3D {
>     /* Field in struct user_gcs.  */
>     "gcs_features_enabled",
> @@ -4136,6 +4141,10 @@ aarch64_features_from_target_desc (const struct= target_desc *tdesc)
>     features.fpmr =3D (tdesc_find_feature (tdesc, = "org.gnu.gdb.aarch64.fpmr")
>            = ;       !=3D nullptr);
>  
> +  /* Check for POE feature.  */
> +  features.poe =3D (tdesc_find_feature (tdesc, "org.gnu.gdb= .aarch64.poe")
> +           &nb= sp;   !=3D nullptr);
> +
>     return features;
>   }
>  
> @@ -4556,6 +4565,19 @@ aarch64_gdbarch_init (struct gdbarch_info info,= struct gdbarch_list *arches)
>            = ;            &n= bsp;            = ;     fpmr_regnum, "fpmr");
>       }
>  
> +  int poe_regnum =3D -1;
> +  const struct tdesc_feature *feature_poe
> +      =3D tdesc_find_feature (tdesc, "o= rg.gnu.gdb.aarch64.poe");
> +  if (feature_poe !=3D nullptr)
> +    {
> +      poe_regnum =3D num_regs;
> +      for (i =3D 0; i < ARRAY_SIZE (aarch= 64_poe_register_names); i++)
> +     valid_p &=3D tdesc_numbered_register (fe= ature_poe, tdesc_data.get (),
> +           &nb= sp;            =             &nb= sp;    poe_regnum + i,
> +           &nb= sp;            =             &nb= sp;    aarch64_poe_register_names[i]);
> +      num_regs++;
> +    }
> +
>     int first_sme_regnum =3D -1;
>     int first_sme2_regnum =3D -1;
>     int first_sme_pseudo_regnum =3D -1;
> @@ -4756,6 +4778,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, = struct gdbarch_list *arches)
>     tdep->gcs_reg_base =3D first_gcs_regnum; >     tdep->gcs_linux_reg_base =3D first_gcs_linu= x_regnum;
>     tdep->fpmr_regnum =3D fpmr_regnum;
> +  tdep->poe_regnum =3D poe_regnum;
>  
>     /* Set the SME register set details.  The= pseudo-registers will be adjusted
>        later.  */
> diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
> index dff05a08f84..3c5d10beee5 100644
> --- a/gdb/aarch64-tdep.h
> +++ b/gdb/aarch64-tdep.h
> @@ -208,6 +208,16 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base >       return gcs_linux_reg_base !=3D -1;=
>     }
>  
> +  /* POE register.  This is -1 if no POE feature is availab= le.  */
> +  int poe_regnum =3D -1;
> +
> +  /* Returns true if the target supports the POE feature.  = */
> +  bool
> +  has_poe () const
> +  {
> +    return poe_regnum !=3D -1;
> +  }
> +
>     /* First FPMR register.  This is -1 if FP= MR is not supported.  */
>     int fpmr_regnum =3D -1;
>  
> diff --git a/gdb/arch/aarch64-poe-linux.h b/gdb/arch/aarch64-poe-linux= .h
> new file mode 100644
> index 00000000000..8623fa43b54
> --- /dev/null
> +++ b/gdb/arch/aarch64-poe-linux.h
> @@ -0,0 +1,29 @@
> +/* Common Linux target-dependent definitions for AArch64 POE
> +
> +   Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +   This file is part of GDB.
> +
> +   This program is free software; you can redistribute it a= nd/or modify
> +   it under the terms of the GNU General Public License as = published by
> +   the Free Software Foundation; either version 3 of the Li= cense, or
> +   (at your option) any later version.
> +
> +   This program is distributed in the hope that it will be = useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warra= nty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.&nbs= p; See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Publi= c License
> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.&nbs= p; */
> +
> +#ifndef GDB_ARCH_AARCH64_POE_LINUX_H
> +#define GDB_ARCH_AARCH64_POE_LINUX_H
> +
> +/* Feature check for Permission Overlay Extension.  */
> +#define AARCH64_HWCAP2_POE (1ULL << 63)
> +
> +/* Data or instruction abort caused by Protection Key Violation. = ; */
> +#define AARCH64_SEGV_PKUERR 4
> +
> +#endif /* GDB_ARCH_AARCH64_POE_LINUX_H.  */
> diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c
> index 2401a325b7b..a567938d06d 100644
> --- a/gdb/arch/aarch64.c
> +++ b/gdb/arch/aarch64.c
> @@ -28,6 +28,7 @@
>   #include "../features/aarch64-sme2.c"
>   #include "../features/aarch64-tls.c"
>   #include "../features/aarch64-gcs.c"
> +#include "../features/aarch64-poe.c"
>   #include "../features/aarch64-gcs-linux.c"
>  
>   /* See arch/aarch64.h.  */
> @@ -77,6 +78,9 @@ aarch64_create_target_description (const aarch64_fea= tures &features)
>     if (features.fpmr)
>       regnum =3D create_feature_aarch64_= fpmr (tdesc.get (), regnum);
>  
> +  if (features.poe)
> +    regnum =3D create_feature_aarch64_poe (tdesc.get (= ), regnum);
> +
>     return tdesc;
>   }
>  
> diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
> index cf7318cbe74..ba90d55c3bb 100644
> --- a/gdb/arch/aarch64.h
> +++ b/gdb/arch/aarch64.h
> @@ -35,6 +35,8 @@ struct aarch64_features
>     bool pauth =3D false;
>     bool mte =3D false;
>     bool fpmr =3D false;
> +  /* Whether the Permission Overlay Extension (FEAT_S1POE) is su= pported.  */
> +  bool poe =3D false;
>  
>     /* A positive TLS value indicates the number o= f TLS registers available.  */
>     uint8_t tls =3D 0;
> @@ -70,7 +72,8 @@ inline bool operator=3D=3D(const aarch64_features &a= mp;lhs, const aarch64_features &rhs)
>       && lhs.sme2 =3D=3D rhs.sme= 2
>       && lhs.gcs =3D=3D rhs.gcs<= br> >       && lhs.gcs_linux =3D=3D rh= s.gcs_linux
> -    && lhs.fpmr =3D=3D rhs.fpmr;
> +    && lhs.fpmr =3D=3D rhs.fpmr
> +    && lhs.poe =3D=3D rhs.poe;
>   }
>  
>   namespace std
> @@ -103,6 +106,9 @@ namespace std
>  
>         /* FPMR feature. = */
>         h =3D h << 1 | f= eatures.fpmr;
> +
> +      /* POE feature.  */
> +      h =3D h << 1 | features.poe;
>         return h;
>       }
>     };
> diff --git a/gdb/features/Makefile b/gdb/features/Makefile
> index 161a7453d66..cc77e5bb652 100644
> --- a/gdb/features/Makefile
> +++ b/gdb/features/Makefile
> @@ -207,6 +207,7 @@ FEATURE_XMLFILES =3D aarch64-core.xml \
>        aarch64-pauth.xml \
>        aarch64-mte.xml \
>        aarch64-gcs.xml \
> +     aarch64-poe.xml \
>        aarch64-gcs-linux.xml \
>        arc/v1-core.xml \
>        arc/v1-aux.xml \
> diff --git a/gdb/features/aarch64-poe.c b/gdb/features/aarch64-poe.c > new file mode 100644
> index 00000000000..4bd795e9fe6
> --- /dev/null
> +++ b/gdb/features/aarch64-poe.c
> @@ -0,0 +1,68 @@
> +/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set r= o:
> +  Original: aarch64-poe.xml */
> +
> +#include "gdbsupport/tdesc.h"
> +
> +static int
> +create_feature_aarch64_poe (struct target_desc *result, long regnum)<= br> > +{
> +  struct tdesc_feature *feature;
> +
> +  feature =3D tdesc_create_feature (result, "org.gnu.gdb.aa= rch64.poe");
> +  tdesc_type_with_fields *type_with_fields;
> +  type_with_fields =3D tdesc_create_enum (feature, "por_el0= _fmt", 4);
> +  tdesc_add_enum_value (type_with_fields, 0, "---"); > +  tdesc_add_enum_value (type_with_fields, 1, "r--"); > +  tdesc_add_enum_value (type_with_fields, 2, "--x"); > +  tdesc_add_enum_value (type_with_fields, 3, "r-x"); > +  tdesc_add_enum_value (type_with_fields, 4, "-w-"); > +  tdesc_add_enum_value (type_with_fields, 5, "rw-"); > +  tdesc_add_enum_value (type_with_fields, 6, "-wx"); > +  tdesc_add_enum_value (type_with_fields, 7, "rwx"); > +  tdesc_add_enum_value (type_with_fields, 8, "???"); > +  tdesc_add_enum_value (type_with_fields, 9, "???"); > +  tdesc_add_enum_value (type_with_fields, 10, "???");<= br> > +  tdesc_add_enum_value (type_with_fields, 11, "???");<= br> > +  tdesc_add_enum_value (type_with_fields, 12, "???");<= br> > +  tdesc_add_enum_value (type_with_fields, 13, "???");<= br> > +  tdesc_add_enum_value (type_with_fields, 14, "???");<= br> > +  tdesc_add_enum_value (type_with_fields, 15, "???");<= br> > +
> +  type_with_fields =3D tdesc_create_flags (feature, "por_el= 0_flags", 8);
> +  tdesc_type *field_type;
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P15", 6= 0, 63, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P14", 5= 6, 59, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P13", 5= 2, 55, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P12", 4= 8, 51, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P11", 4= 4, 47, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P10", 4= 0, 43, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P9", 36= , 39, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P8", 32= , 35, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P7", 28= , 31, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P6", 24= , 27, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P5", 20= , 23, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P4", 16= , 19, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P3", 12= , 15, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P2", 8,= 11, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P1", 4,= 7, field_type);
> +  field_type =3D tdesc_named_type (feature, "por_el0_fmt&qu= ot;);
> +  tdesc_add_typed_bitfield (type_with_fields, "P0", 0,= 3, field_type);
> +
> +  tdesc_create_reg (feature, "por_el0", regnum++, 1, &= quot;system", 64, "por_el0_flags");
> +  return regnum;
> +}
> diff --git a/gdb/features/aarch64-poe.xml b/gdb/features/aarch64-poe.x= ml
> new file mode 100644
> index 00000000000..58fc4f80d5c
> --- /dev/null
> +++ b/gdb/features/aarch64-poe.xml
> @@ -0,0 +1,47 @@
> +<?xml version=3D"1.0"?>
> +<!-- Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +     Copying and distribution of this file, with = or without modification,
> +     are permitted in any medium without royalty = provided the copyright
> +     notice and this notice are preserved.  = -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name=3D"org.gnu.gdb.aarch64.poe">
> +  <enum id=3D"por_el0_fmt" size=3D"4">=
> +    <evalue name=3D"---" value=3D"0&= quot;/>
> +    <evalue name=3D"r--" value=3D"1&= quot;/>
> +    <evalue name=3D"--x" value=3D"2&= quot;/>
> +    <evalue name=3D"r-x" value=3D"3&= quot;/>
> +    <evalue name=3D"-w-" value=3D"4&= quot;/>
> +    <evalue name=3D"rw-" value=3D"5&= quot;/>
> +    <evalue name=3D"-wx" value=3D"6&= quot;/>
> +    <evalue name=3D"rwx" value=3D"7&= quot;/>
> +    <evalue name=3D"???" value=3D"8&= quot;/>
> +    <evalue name=3D"???" value=3D"9&= quot;/>
> +    <evalue name=3D"???" value=3D"10= "/>
> +    <evalue name=3D"???" value=3D"11= "/>
> +    <evalue name=3D"???" value=3D"12= "/>
> +    <evalue name=3D"???" value=3D"13= "/>
> +    <evalue name=3D"???" value=3D"14= "/>
> +    <evalue name=3D"???" value=3D"15= "/>
> +  </enum>
> +  <flags id=3D"por_el0_flags" size=3D"8"&= gt;
> +    <field name=3D"P15" start=3D"60&= quot; end=3D"63" type=3D"por_el0_fmt"/>
> +    <field name=3D"P14" start=3D"56&= quot; end=3D"59" type=3D"por_el0_fmt"/>
> +    <field name=3D"P13" start=3D"52&= quot; end=3D"55" type=3D"por_el0_fmt"/>
> +    <field name=3D"P12" start=3D"48&= quot; end=3D"51" type=3D"por_el0_fmt"/>
> +    <field name=3D"P11" start=3D"44&= quot; end=3D"47" type=3D"por_el0_fmt"/>
> +    <field name=3D"P10" start=3D"40&= quot; end=3D"43" type=3D"por_el0_fmt"/>
> +    <field name=3D"P9" start=3D"36&q= uot; end=3D"39" type=3D"por_el0_fmt"/>
> +    <field name=3D"P8" start=3D"32&q= uot; end=3D"35" type=3D"por_el0_fmt"/>
> +    <field name=3D"P7" start=3D"28&q= uot; end=3D"31" type=3D"por_el0_fmt"/>
> +    <field name=3D"P6" start=3D"24&q= uot; end=3D"27" type=3D"por_el0_fmt"/>
> +    <field name=3D"P5" start=3D"20&q= uot; end=3D"23" type=3D"por_el0_fmt"/>
> +    <field name=3D"P4" start=3D"16&q= uot; end=3D"19" type=3D"por_el0_fmt"/>
> +    <field name=3D"P3" start=3D"12&q= uot; end=3D"15" type=3D"por_el0_fmt"/>
> +    <field name=3D"P2" start=3D"8&qu= ot; end=3D"11" type=3D"por_el0_fmt"/>
> +    <field name=3D"P1" start=3D"4&qu= ot; end=3D"7" type=3D"por_el0_fmt"/>
> +    <field name=3D"P0" start=3D"0&qu= ot; end=3D"3" type=3D"por_el0_fmt"/>
> +  </flags>
> +  <reg name=3D"por_el0" bitsize=3D"64" ty= pe=3D"por_el0_flags" group=3D"system"/>
> +</feature>
> diff --git a/gdb/nat/aarch64-poe-linux.h b/gdb/nat/aarch64-poe-linux.h=
> new file mode 100644
> index 00000000000..f3d0256da3f
> --- /dev/null
> +++ b/gdb/nat/aarch64-poe-linux.h
> @@ -0,0 +1,29 @@
> +/* Common native Linux definitions for AArch64 Permission Overlay Ext= ension.
> +
> +   Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +   This file is part of GDB.
> +
> +   This program is free software; you can redistribute it a= nd/or modify
> +   it under the terms of the GNU General Public License as = published by
> +   the Free Software Foundation; either version 3 of the Li= cense, or
> +   (at your option) any later version.
> +
> +   This program is distributed in the hope that it will be = useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warra= nty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.&nbs= p; See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Publi= c License
> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.&nbs= p; */
> +
> +#include <asm/hwcap.h>

Shouldn=B4t the above be inside the include guard?

> +#ifndef GDB_NAT_AARCH64_POE_LINUX_H
> +#define GDB_NAT_AARCH64_POE_LINUX_H
> +
> +/* Feature check for Permission Overlay Extension.  */
> +#ifndef HWCAP2_POE
> +#define HWCAP2_POE (1ULL << 63)
> +#endif /* HWCAP2_POE.  */
> +
> +#endif /* GDB_NAT_AARCH64_POE_LINUX_H.  */

--_000_AS8PR08MB10099E7285C79E152E1D56E8D9BC02AS8PR08MB10099eu_--