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15.20.4264.026; Tue, 29 Jun 2021 09:11:41 +0000 To: Alan Hayward , Mike Frysinger Subject: Re: [PATCH] sim: arm: add support for handling core dumps Thread-Topic: [PATCH] sim: arm: add support for handling core dumps Thread-Index: AQHXZmb5gmbcrCVdO0K/IHyrHhdMwqsfXkeAgAPG4ACAB5lnOw== Date: Tue, 29 Jun 2021 09:11:41 +0000 Message-ID: References: <20210118110922.GT265215@embecosm.com> <0327e6b6-2a4e-cf4f-333c-5f3cde18c49c@linaro.org> ,<36F6111C-FF52-4002-8B5F-5758F09F1859@arm.com> In-Reply-To: <36F6111C-FF52-4002-8B5F-5758F09F1859@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [62.13.16.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7333c07f-0d3e-40c4-790d-08d93adde896 x-ms-traffictypediagnostic: AM9PR10MB4087: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 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AkL90gsf0sQ+MGmO9K/RNbNW9QnXUMUfIYTwrnsDCiJwI3wm+fG6XfabStKDfrLkri1/qTY7IVHT2x92DIJNUrzF/hQZ45nKjBR0SJlgX9AOlgqxsyDL1SMAiwS5ZkOY X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR10MB4087 X-Proofpoint-GUID: O65w4oXy_G-d5Epjl4yPScFU26C_hy2e X-Proofpoint-ORIG-GUID: O65w4oXy_G-d5Epjl4yPScFU26C_hy2e X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-29_05:2021-06-25, 2021-06-29 signatures=0 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Fredrik Hederstierna via Gdb-patches Reply-To: Fredrik Hederstierna Cc: Simon Marchi , "gdb-patches@sourceware.org" , Paul Mathieu Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" I reviewed comments and decided to make a complete retake on this.=0A= Here is a patch that adds IDs for D0-D31, then let any calling ARM simulato= r implementation handle the results.=0A= =0A= I tested 'gcore' on target sim for ARM on this, and it worked well on my te= sts.=0A= I also understood better why I got these 4GB corefiles, since I did not set= SP (ARM simulator is not supporting Cortex),=0A= so as SP was 0, then after some calls, the SP was like 0xFFFFFFxx, so stack= was like 4GB up in memory space.=0A= When I added code lines at start to set SP to a lower address, the corefile= was getting smaller correct size.=0A= =0A= BR Fredrik=0A= =0A= =0A= diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c=0A= index 857a52a9a51..2593d89269f 100644=0A= --- a/gdb/arm-tdep.c=0A= +++ b/gdb/arm-tdep.c=0A= @@ -4246,6 +4246,9 @@ arm_register_sim_regno (struct gdbarch *gdbarch, int = regnum)=0A= if (regnum >=3D ARM_WCGR0_REGNUM && regnum <=3D ARM_WCGR7_REGNUM)=0A= return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;=0A= =0A= + if (regnum >=3D ARM_D0_REGNUM && regnum <=3D ARM_FPSCR_REGNUM)=0A= + return regnum - ARM_D0_REGNUM + SIM_ARM_D0_REGNUM;=0A= +=0A= if (reg < NUM_GREGS)=0A= return SIM_ARM_R0_REGNUM + reg;=0A= reg -=3D NUM_GREGS;=0A= diff --git a/include/gdb/sim-arm.h b/include/gdb/sim-arm.h=0A= index 8aafa045a0e..28d336be525 100644=0A= --- a/include/gdb/sim-arm.h=0A= +++ b/include/gdb/sim-arm.h=0A= @@ -98,7 +98,41 @@ enum sim_arm_regs=0A= SIM_ARM_IWMMXT_COP1R12_REGNUM,=0A= SIM_ARM_IWMMXT_COP1R13_REGNUM,=0A= SIM_ARM_IWMMXT_COP1R14_REGNUM,=0A= - SIM_ARM_IWMMXT_COP1R15_REGNUM=0A= + SIM_ARM_IWMMXT_COP1R15_REGNUM,=0A= + SIM_ARM_D0_REGNUM,=0A= + SIM_ARM_D1_REGNUM,=0A= + SIM_ARM_D2_REGNUM,=0A= + SIM_ARM_D3_REGNUM,=0A= + SIM_ARM_D4_REGNUM,=0A= + SIM_ARM_D5_REGNUM,=0A= + SIM_ARM_D6_REGNUM,=0A= + SIM_ARM_D7_REGNUM,=0A= + SIM_ARM_D8_REGNUM,=0A= + SIM_ARM_D9_REGNUM,=0A= + SIM_ARM_D10_REGNUM,=0A= + SIM_ARM_D11_REGNUM,=0A= + SIM_ARM_D12_REGNUM,=0A= + SIM_ARM_D13_REGNUM,=0A= + SIM_ARM_D14_REGNUM,=0A= + SIM_ARM_D15_REGNUM,=0A= + SIM_ARM_D16_REGNUM,=0A= + SIM_ARM_D17_REGNUM,=0A= + SIM_ARM_D18_REGNUM,=0A= + SIM_ARM_D19_REGNUM,=0A= + SIM_ARM_D20_REGNUM,=0A= + SIM_ARM_D21_REGNUM,=0A= + SIM_ARM_D22_REGNUM,=0A= + SIM_ARM_D23_REGNUM,=0A= + SIM_ARM_D24_REGNUM,=0A= + SIM_ARM_D25_REGNUM,=0A= + SIM_ARM_D26_REGNUM,=0A= + SIM_ARM_D27_REGNUM,=0A= + SIM_ARM_D28_REGNUM,=0A= + SIM_ARM_D29_REGNUM,=0A= + SIM_ARM_D30_REGNUM,=0A= + SIM_ARM_D31_REGNUM,=0A= + SIM_ARM_FPSCR_REGNUM,=0A= + SIM_ARM_NUM_REGS=0A= };=0A= =0A= #endif=0A= diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c=0A= index e697d55a6b5..69c5905b1ff 100644=0A= --- a/sim/arm/wrapper.c=0A= +++ b/sim/arm/wrapper.c=0A= @@ -418,6 +418,12 @@ arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *me= mory, int length)=0A= {=0A= init ();=0A= =0A= + if (rn >=3D SIM_ARM_NUM_REGS)=0A= + {=0A= + sim_io_eprintf (CPU_STATE (cpu), "Invalid register %d (register stor= e ignored)\n", rn);=0A= + return 0;=0A= + }=0A= +=0A= switch ((enum sim_arm_regs) rn)=0A= {=0A= case SIM_ARM_R0_REGNUM:=0A= @@ -509,7 +515,47 @@ arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *me= mory, int length)=0A= case SIM_ARM_IWMMXT_COP1R13_REGNUM:=0A= case SIM_ARM_IWMMXT_COP1R14_REGNUM:=0A= case SIM_ARM_IWMMXT_COP1R15_REGNUM:=0A= - return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, mem= ory);=0A= + if (state->is_iWMMXt)=0A= + {=0A= + return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM,= memory);=0A= + }=0A= + return 0;=0A= +=0A= + case SIM_ARM_D0_REGNUM:=0A= + case SIM_ARM_D1_REGNUM:=0A= + case SIM_ARM_D2_REGNUM:=0A= + case SIM_ARM_D3_REGNUM:=0A= + case SIM_ARM_D4_REGNUM:=0A= + case SIM_ARM_D5_REGNUM:=0A= + case SIM_ARM_D6_REGNUM:=0A= + case SIM_ARM_D7_REGNUM:=0A= + case SIM_ARM_D8_REGNUM:=0A= + case SIM_ARM_D9_REGNUM:=0A= + case SIM_ARM_D10_REGNUM:=0A= + case SIM_ARM_D11_REGNUM:=0A= + case SIM_ARM_D12_REGNUM:=0A= + case SIM_ARM_D13_REGNUM:=0A= + case SIM_ARM_D14_REGNUM:=0A= + case SIM_ARM_D15_REGNUM:=0A= + case SIM_ARM_D16_REGNUM:=0A= + case SIM_ARM_D17_REGNUM:=0A= + case SIM_ARM_D18_REGNUM:=0A= + case SIM_ARM_D19_REGNUM:=0A= + case SIM_ARM_D20_REGNUM:=0A= + case SIM_ARM_D21_REGNUM:=0A= + case SIM_ARM_D22_REGNUM:=0A= + case SIM_ARM_D23_REGNUM:=0A= + case SIM_ARM_D24_REGNUM:=0A= + case SIM_ARM_D25_REGNUM:=0A= + case SIM_ARM_D26_REGNUM:=0A= + case SIM_ARM_D27_REGNUM:=0A= + case SIM_ARM_D28_REGNUM:=0A= + case SIM_ARM_D29_REGNUM:=0A= + case SIM_ARM_D30_REGNUM:=0A= + case SIM_ARM_D31_REGNUM:=0A= + case SIM_ARM_FPSCR_REGNUM:=0A= + /* The current GDB ARM simulator does not support D0-D31 nor FPSCR. = */=0A= + return 0;=0A= =0A= default:=0A= return 0;=0A= @@ -526,6 +572,12 @@ arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *me= mory, int length)=0A= =0A= init ();=0A= =0A= + if (rn >=3D SIM_ARM_NUM_REGS)=0A= + {=0A= + sim_io_eprintf (CPU_STATE (cpu), "Invalid register %d (register fetc= h ignored)\n", rn);=0A= + return 0;=0A= + }=0A= +=0A= switch ((enum sim_arm_regs) rn)=0A= {=0A= case SIM_ARM_R0_REGNUM:=0A= @@ -619,7 +671,47 @@ arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *me= mory, int length)=0A= case SIM_ARM_IWMMXT_COP1R13_REGNUM:=0A= case SIM_ARM_IWMMXT_COP1R14_REGNUM:=0A= case SIM_ARM_IWMMXT_COP1R15_REGNUM:=0A= - return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, mem= ory);=0A= + if (state->is_iWMMXt)=0A= + {=0A= + return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM,= memory);=0A= + }=0A= + return 0;=0A= +=0A= + case SIM_ARM_D0_REGNUM:=0A= + case SIM_ARM_D1_REGNUM:=0A= + case SIM_ARM_D2_REGNUM:=0A= + case SIM_ARM_D3_REGNUM:=0A= + case SIM_ARM_D4_REGNUM:=0A= + case SIM_ARM_D5_REGNUM:=0A= + case SIM_ARM_D6_REGNUM:=0A= + case SIM_ARM_D7_REGNUM:=0A= + case SIM_ARM_D8_REGNUM:=0A= + case SIM_ARM_D9_REGNUM:=0A= + case SIM_ARM_D10_REGNUM:=0A= + case SIM_ARM_D11_REGNUM:=0A= + case SIM_ARM_D12_REGNUM:=0A= + case SIM_ARM_D13_REGNUM:=0A= + case SIM_ARM_D14_REGNUM:=0A= + case SIM_ARM_D15_REGNUM:=0A= + case SIM_ARM_D16_REGNUM:=0A= + case SIM_ARM_D17_REGNUM:=0A= + case SIM_ARM_D18_REGNUM:=0A= + case SIM_ARM_D19_REGNUM:=0A= + case SIM_ARM_D20_REGNUM:=0A= + case SIM_ARM_D21_REGNUM:=0A= + case SIM_ARM_D22_REGNUM:=0A= + case SIM_ARM_D23_REGNUM:=0A= + case SIM_ARM_D24_REGNUM:=0A= + case SIM_ARM_D25_REGNUM:=0A= + case SIM_ARM_D26_REGNUM:=0A= + case SIM_ARM_D27_REGNUM:=0A= + case SIM_ARM_D28_REGNUM:=0A= + case SIM_ARM_D29_REGNUM:=0A= + case SIM_ARM_D30_REGNUM:=0A= + case SIM_ARM_D31_REGNUM:=0A= + case SIM_ARM_FPSCR_REGNUM:=0A= + /* The current GDB ARM simulator does not support D0-D31 nor FPSCR. = */=0A= + return 0;=0A= =0A= default:=0A= return 0;=0A= =0A= =0A=