[PATCH] sim: arm: add support for handling core dumps

Fredrik Hederstierna via Gdb-patches
2021-06-21T06:31:22Z

The ARM simulator does not support all registers, and also crash in case of entering zero length when fetching registers.
This patch allow gcore to also work in ARM simulator, though by default it seems to dump full memory space 4GB, so core files get very large, though seems to work ok anyhow.

BR Fredrik

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 857a52a9a51..2820e456cf7 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -4246,6 +4246,10 @@ arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;

+ /* The current GDB ARM simulator does not support D0-D31 nor FPSCR. */
+ if (regnum >= ARM_D0_REGNUM && regnum <= ARM_FPSCR_REGNUM)
+ return -1;
+
if (reg < NUM_GREGS)
return SIM_ARM_R0_REGNUM + reg;
reg -= NUM_GREGS;
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index e697d55a6b5..2a8a539b939 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -526,6 +526,10 @@ arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)

init ();

+ /* Check that memory and length are valid before fetching the register. */
+ if ((memory == NULL) || (length == 0))
+ return 0;
+
switch ((enum sim_arm_regs) rn)
{
case SIM_ARM_R0_REGNUM: