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Sun, 6 Sep 2020 09:27:26 +0000 From: Fredrik Hederstierna To: Alan Hayward CC: "gdb-patches\\@sourceware.org" , nd , James-Adam Renquinha Henri Subject: Re: [PATCH] Fix exception stack unwinding for ARM Cortex-M Thread-Topic: [PATCH] Fix exception stack unwinding for ARM Cortex-M Thread-Index: AQHWfd9KZNChspL/gEKRcBh3+cqQUKlVXOWAgAYD57w= Date: Sun, 6 Sep 2020 09:27:26 +0000 Message-ID: References: <790E863F-88F4-47D7-A70A-FA22779ACC2A@arm.com> , <04F0F9D3-6A7D-4F6E-8AE7-93F360CEEA91@arm.com> In-Reply-To: <04F0F9D3-6A7D-4F6E-8AE7-93F360CEEA91@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [81.236.17.7] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c73c5dee-9c3b-4ea7-ba35-08d8524711b6 x-ms-traffictypediagnostic: AM7PR10MB3176: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: rbG7kF+xtozQs6CHF3oNPGgM71j0xP9/l1eGXQ1Zz8b9+cwyoommNz/z1pYPUk010Gc2ZY9PFfXl8gv+oOOB4OCcQEq0z57ktiDXwVChI5sGBKkIfNEf9ShEmn2zHo3C/I0wBfRjf/TWrCPmbXJyHJA/ajLBsDovlB2Rbeo8mIJ9cIxek1uHmACgCkVIqRN5/qNCxhUhQ/e4nKVPDqHddCxcwPaKE66zOU7lMrg2Ks4ntJivKPMVGRLKl8eaBOJjNOorMCl5nysYFhRWw6gZwapRUAjyv7sSlcP6WryOWWgSdHndDs7y3lLRklegQh5BLQw7pdurwiswoTlKYkvrHw== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Hi,=0A= I updated that patch to address your comments, see below and attached patch= take2=0A= =0A= > From: Alan Hayward =0A= > Sent: Wednesday, September 2, 2020 3:24 PM=0A= > To: Fredrik Hederstierna =0A= =0A= > How easy is it to compile a binary that exhibits this behaviour? If so th= en a=0A= > test in testsuite/gdb.arch/ would be nice. For reference, aarch64-sighand= ler-regs.exp=0A= > is a similar test but for AArch64.=0A= =0A= I have not had time to further look into this, its probably possible to add= such a test case, but I have no possibility to do this currently unfortuna= tely.=0A= =0A= > Have you signed the copyright assignment?=0A= =0A= Yes, to my understanding everything is clear.=0A= =0A= >> diff --git a/gdb/ChangeLog b/gdb/ChangeLog=0A= >> index 1ff47c3355..1d80e8cfc8 100644=0A= >> --- a/gdb/ChangeLog=0A= >> +++ b/gdb/ChangeLog=0A= >> @@ -1,3 +1,9 @@=0A= >> +2020-08-29=A0 Fredrik Hederstierna=A0 =0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 Adam Renquinha =0A= >> +=0A= >> +=A0=A0=A0=A0 * arm-tdep.c (arm_m_exception_cache): Try use correct stac= k=0A= >> +=A0=A0=A0=A0 pointer and stack frame offset when unwinding.=0A= >> +=0A= >=0A= > Ideally this part should be left separate from the patch as to prevent=0A= > merge issues.=0A= =0A= Ok, removed from patch.=0A= =0A= >> +=A0 /* Check if main stack was used.=A0 */=0A= >> +=A0 main_stack_used =3D ((lr & 0xf) !=3D 0xd);=0A= >=0A= > This took me a while to confirm. Could you mention that you are checking = for=0A= > SPSEL in the comment. Also, I wonder if it=92s worth checking the other b= its in lr.=0A= > Yes they should be all ones in either case. But I=92d rather be a little = cautious.=0A= > Only go into the else case if all the bits are correct.=0A= =0A= Ok, added more clear comments and more strict bit checking.=0A= =0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* Thread (process) stack could not be fetc= hed,=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 give warning and exit.=A0 */=0A= >> +=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0 warning (_("no PSP thread stack unwinding s= upported, exiting."));=0A= >=0A= > I don=92t think you mean exit. Maybe just remove =93exiting=94 from the s= tring.=0A= =0A= Ok, removed 'exiting'=0A= =0A= >> +=A0=A0=A0=A0=A0 /* This code does not take into account the lazy stacki= ng, see "Lazy=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 context save of FP state", in B1.5.7, also ARM= AN298, supported=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 by Cortex-M4F architecture. Give a warning and= try do best effort.=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 To fully handle this the FPCCR register (Float= ing-point Context=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 Control Register) needs to be read out and the= bits ASPEN and LSPEN=0A= >> +=A0=A0=A0=A0=A0=A0=A0=A0 could be checked to setup correct lazy stacked= FP registers.=A0 */=0A= >> +=0A= >> +=A0=A0=A0=A0=A0 warning (_("no FPU lazy stack unwinding supported, chec= k FPCCR."));=0A= >=0A= > This means that we will always get a warning if the extended frame is use= d.=0A= > I=92d rather that didn=92t happen.=0A= > How easy would be be to check the FPCCR register and then give a warning = only if=0A= > lazy stacking is being used?=0A= =0A= Maybe its possible, but have to time to solve this currently, added memory = address of FPCCR,=0A= its not a register, but probably possible to do memory reading to dig deepe= r into this.=0A= Removed warning.=0A= =0A= >> +=A0=A0=A0=A0=A0 /* Basic frame type used.=A0 */=0A= >> +=A0=A0=A0=A0=A0 cache->prev_sp =3D unwound_sp + 32;=0A= >=0A= > The mix of hex and decimal in the function is a little glaring.=0A= > Could you switch this one to 0x20.=0A= =0A= Ok, fixed.=0A= =0A= =0A= Here is ChangeLog, separated, new patch variant attached.=0A= =0A= 2020-09-06 Fredrik Hederstierna =0A= Adam Renquinha =0A= =0A= * arm-tdep.c (arm_m_exception_cache): Try use correct stack=0A= pointer and stack frame offset when unwinding.=0A= =0A= =0A= BR Fredrik=0A= --_002_AM6PR10MB2150A9E153F1FA595A4349FCEF2B0AM6PR10MB2150EURP_ Content-Type: text/x-patch; name="gdb-cortex-m-exception-unwind-fix2.patch" Content-Description: gdb-cortex-m-exception-unwind-fix2.patch Content-Disposition: attachment; filename="gdb-cortex-m-exception-unwind-fix2.patch"; size=7024; creation-date="Sun, 06 Sep 2020 09:27:14 GMT"; modification-date="Sun, 06 Sep 2020 09:27:14 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2dkYi9hcm0tdGRlcC5jIGIvZ2RiL2FybS10ZGVwLmMKaW5kZXggMDc0ZWVk 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