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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT027.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3731 X-Spam-Status: No, score=-17.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Jul 2020 15:00:22 -0000 --===============7607632271222351956== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Enable displaced stepping over a BR/BLR instruction Displaced stepping over an instruction executes a instruction in a scratch area and then manually fixes up the PC address to leave execution where it would have been if the instruction were in its original location. The BR instruction does not need modification in order to run correctly at a different address, but the displaced step fixup method should not manually adjust the PC since the BR instruction sets that value already. The BLR instruction should also avoid such a fixup, but must also have the link register modified to point to just after the original code location rather than back to the scratch location. This patch adds the above functionality. We add this functionality by modifying aarch64_displaced_step_others rather than by adding a new visitor method to aarch64_insn_visitor. We choose this since it seems that visitor approach is designed specifically for PC relative instructions (which must always be modified when executed in a different location). It seems that the BR and BLR instructions are more like the RET instruction which is already handled specially in aarch64_displaced_step_others. This also means the gdbserver code to relocate an instruction when creating a fast tracepoint does not need to be modified, since nothing special is needed for the BR and BLR instructions there. Manually tested on AArch64 (it doesn't look like there are tests for displaced stepping on the other instructions that are manually handled, so I figured adding a testcase for BR and BLR would be out of place). ------##### Observed (mis)behaviour before was that displaced stepping over a BR or BLR instruction would not execute the function they called. Most easily seen by putting a breakpoint with a condition on such an instruction and a print statement in the functions they called. When run with the breakpoint enabled the function is not called and "numargs called" is not printed. When run with the breakpoint disabled the function is called and the message is printed. --- GDB Session hw-a20-10:gcc-source [15:57:14] % gdb ../using-blr Reading symbols from ../using-blr...done. (gdb) disassemble blr_call_value Dump of assembler code for function blr_call_value: ... 0x0000000000400560 <+28>: blr x2 ... 0x00000000004005b8 <+116>: ret End of assembler dump. (gdb) break *0x0000000000400560 Breakpoint 1 at 0x400560: file ../using-blr.c, line 22. (gdb) condition 1 10 == 0 (gdb) run Starting program: /home/matmal01/using-blr [Inferior 1 (process 33279) exited with code 012] (gdb) disable 1 (gdb) run Starting program: /home/matmal01/using-blr numargs called [Inferior 1 (process 33289) exited with code 012] (gdb) Test program: ---- using-blr ---- \#include typedef int (foo) (int, int); typedef void (bar) (int, int); struct sls_testclass { foo *x; bar *y; int left; int right; }; __attribute__ ((noinline)) int blr_call_value (struct sls_testclass x) { int retval = x.x(x.left, x.right); if (retval % 10) return 100; return 9; } __attribute__ ((noinline)) int blr_call (struct sls_testclass x) { x.y(x.left, x.right); if (x.left % 10) return 100; return 9; } int numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right) { printf("numargs called\n"); return 10; } void altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right) { printf("altfunc called\n"); } int main(int argc, char **argv) { struct sls_testclass x = { .x = numargs, .y = altfunc, .left = 1, .right = 2 }; if (argc > 2) { blr_call (x); } else blr_call_value (x); return 10; } ------ gdb/ChangeLog: 2020-07-03 Matthew Malcomson * aarch64-tdep.c (aarch64_displaced_step_others): Account for BR and BLR instructions. * arch/aarch64-insn.h (enum aarch64_opcodes): Add BR instruction. ############### Attachment also inlined for ease of reply ############### diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 5e7d0d0b8682af04ce4f01fd999d26c9eb459932..640a3e302f8e2b5fac3575e2f37212d40441d318 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2974,15 +2974,22 @@ aarch64_displaced_step_others (const uint32_t insn, struct aarch64_displaced_step_data *dsd = (struct aarch64_displaced_step_data *) data; - aarch64_emit_insn (dsd->insn_buf, insn); - dsd->insn_count = 1; - - if ((insn & 0xfffffc1f) == 0xd65f0000) + uint32_t masked_insn = (insn & 0xfffffc1f); + if (masked_insn == BLR) { - /* RET */ - dsd->dsc->pc_adjust = 0; + /* Emit a BR to the same register and then update LR to the original + address (similar to aarch64_displaced_step_b). */ + aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff); + regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, + data->insn_addr + 4); } else + aarch64_emit_insn (dsd->insn_buf, insn); + dsd->insn_count = 1; + + if (masked_insn == RET || masked_insn == BR || masked_insn == BLR) + dsd->dsc->pc_adjust = 0; + else dsd->dsc->pc_adjust = 4; } diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h index 6a63ce9c2005acd6fe018a12c640f1be01751d6b..6b8721139f8446d82aecac243501d31137c885a5 100644 --- a/gdb/arch/aarch64-insn.h +++ b/gdb/arch/aarch64-insn.h @@ -40,7 +40,9 @@ enum aarch64_opcodes CBNZ = 0x21000000 | B, TBZ = 0x36000000 | B, TBNZ = 0x37000000 | B, + /* BR 1101 0110 0001 1111 0000 00rr rrr0 0000 */ /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */ + BR = 0xd61f0000, BLR = 0xd63f0000, /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */ RET = 0xd65f0000, --===============7607632271222351956== Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="blr-br-displaced-step.patch" ZGlmZiAtLWdpdCBhL2dkYi9hYXJjaDY0LXRkZXAuYyBiL2dkYi9hYXJjaDY0LXRkZXAuYwppbmRl eCA1ZTdkMGQwYjg2ODJhZjA0Y2U0ZjAxZmQ5OTlkMjZjOWViNDU5OTMyLi42NDBhM2UzMDJmOGUy YjVmYWMzNTc1ZTJmMzcyMTJkNDA0NDFkMzE4IDEwMDY0NAotLS0gYS9nZGIvYWFyY2g2NC10ZGVw LmMKKysrIGIvZ2RiL2FhcmNoNjQtdGRlcC5jCkBAIC0yOTc0LDE1ICsyOTc0LDIyIEBAIGFhcmNo NjRfZGlzcGxhY2VkX3N0ZXBfb3RoZXJzIChjb25zdCB1aW50MzJfdCBpbnNuLAogICBzdHJ1Y3Qg YWFyY2g2NF9kaXNwbGFjZWRfc3RlcF9kYXRhICpkc2QKICAgICA9IChzdHJ1Y3QgYWFyY2g2NF9k aXNwbGFjZWRfc3RlcF9kYXRhICopIGRhdGE7CiAKLSAgYWFyY2g2NF9lbWl0X2luc24gKGRzZC0+ aW5zbl9idWYsIGluc24pOwotICBkc2QtPmluc25fY291bnQgPSAxOwotCi0gIGlmICgoaW5zbiAm IDB4ZmZmZmZjMWYpID09IDB4ZDY1ZjAwMDApCisgIHVpbnQzMl90IG1hc2tlZF9pbnNuID0gKGlu c24gJiAweGZmZmZmYzFmKTsKKyAgaWYgKG1hc2tlZF9pbnNuID09IEJMUikKICAgICB7Ci0gICAg ICAvKiBSRVQgKi8KLSAgICAgIGRzZC0+ZHNjLT5wY19hZGp1c3QgPSAwOworICAgICAgLyogRW1p dCBhIEJSIHRvIHRoZSBzYW1lIHJlZ2lzdGVyIGFuZCB0aGVuIHVwZGF0ZSBMUiB0byB0aGUgb3Jp Z2luYWwKKwkgYWRkcmVzcyAoc2ltaWxhciB0byBhYXJjaDY0X2Rpc3BsYWNlZF9zdGVwX2IpLiAg Ki8KKyAgICAgIGFhcmNoNjRfZW1pdF9pbnNuIChkc2QtPmluc25fYnVmLCBpbnNuICYgMHhmZmRm ZmZmZik7CisgICAgICByZWdjYWNoZV9jb29rZWRfd3JpdGVfdW5zaWduZWQgKGRzZC0+cmVncywg QUFSQ0g2NF9MUl9SRUdOVU0sCisJCQkJICAgICAgZGF0YS0+aW5zbl9hZGRyICsgNCk7CiAgICAg fQogICBlbHNlCisgICAgYWFyY2g2NF9lbWl0X2luc24gKGRzZC0+aW5zbl9idWYsIGluc24pOwor ICBkc2QtPmluc25fY291bnQgPSAxOworCisgIGlmIChtYXNrZWRfaW5zbiA9PSBSRVQgfHwgbWFz a2VkX2luc24gPT0gQlIgfHwgbWFza2VkX2luc24gPT0gQkxSKQorICAgIGRzZC0+ZHNjLT5wY19h ZGp1c3QgPSAwOworICBlbHNlCiAgICAgZHNkLT5kc2MtPnBjX2FkanVzdCA9IDQ7CiB9CiAKZGlm ZiAtLWdpdCBhL2dkYi9hcmNoL2FhcmNoNjQtaW5zbi5oIGIvZ2RiL2FyY2gvYWFyY2g2NC1pbnNu LmgKaW5kZXggNmE2M2NlOWMyMDA1YWNkNmZlMDE4YTEyYzY0MGYxYmUwMTc1MWQ2Yi4uNmI4NzIx MTM5Zjg0NDZkODJhZWNhYzI0MzUwMWQzMTEzN2M4ODVhNSAxMDA2NDQKLS0tIGEvZ2RiL2FyY2gv YWFyY2g2NC1pbnNuLmgKKysrIGIvZ2RiL2FyY2gvYWFyY2g2NC1pbnNuLmgKQEAgLTQwLDcgKzQw LDkgQEAgZW51bSBhYXJjaDY0X29wY29kZXMKICAgQ0JOWiAgICAgICAgICAgID0gMHgyMTAwMDAw MCB8IEIsCiAgIFRCWiAgICAgICAgICAgICA9IDB4MzYwMDAwMDAgfCBCLAogICBUQk5aICAgICAg ICAgICAgPSAweDM3MDAwMDAwIHwgQiwKKyAgLyogQlIgICAgICAgICAgICAgMTEwMSAwMTEwIDAw MDEgMTExMSAwMDAwIDAwcnIgcnJyMCAwMDAwICovCiAgIC8qIEJMUiAgICAgICAgICAgIDExMDEg MDExMCAwMDExIDExMTEgMDAwMCAwMHJyIHJycjAgMDAwMCAqLworICBCUiAgICAgICAgICAgICAg PSAweGQ2MWYwMDAwLAogICBCTFIgICAgICAgICAgICAgPSAweGQ2M2YwMDAwLAogICAvKiBSRVQg ICAgICAgICAgICAxMTAxIDAxMTAgMDEwMSAxMTExIDAwMDAgMDByciBycnIwIDAwMDAgKi8KICAg UkVUICAgICAgICAgICAgID0gMHhkNjVmMDAwMCwKCg== --===============7607632271222351956==--