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Fri, 8 Oct 2021 16:04:03 +0000 To: Luis Machado Subject: Re: [PATCH 3/4] [ARM] Refactor pseudo register numbering Thread-Topic: [PATCH 3/4] [ARM] Refactor pseudo register numbering Thread-Index: AQHXufews02uW6YRxUKDkfc+KQjLM6vJSEkA Date: Fri, 8 Oct 2021 16:04:03 +0000 Message-ID: References: <20211005144521.1965198-1-luis.machado@linaro.org> <20211005144521.1965198-4-luis.machado@linaro.org> In-Reply-To: <20211005144521.1965198-4-luis.machado@linaro.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3654.120.0.1.13) Authentication-Results-Original: linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=arm.com; x-ms-publictraffictype: Email X-MS-Office365-Filtering-Correlation-Id: 94a85fd7-c8f8-4d74-3b70-08d98a75447c x-ms-traffictypediagnostic: AS8PR08MB6709:|VI1PR08MB3102: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:2000;OLM:2000; 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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 16:04:11.3625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94a85fd7-c8f8-4d74-3b70-08d98a75447c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3102 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Alan Hayward via Gdb-patches Reply-To: Alan Hayward Cc: Peter Maydell , nd , "gdb-patches\\@sourceware.org" Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" This is similar to AArch64 target, so mostly Lgtm... > On 5 Oct 2021, at 15:45, Luis Machado wrote: >=20 > The pseudo register handling for ARM uses some hardcoded constants to > determine types and names. In preparation to the upcoming MVE support > patch (that will add another pseudo register), this patch refactors and > reorganizes things in order to simplify handling of future pseudo registe= rs. >=20 > We keep track of the first pseudo register number in a group and the numb= er of > pseudo registers in that group. >=20 > Right now we only have the S and Q pseudo registers. Renaming NEON to Q makes sense. Why not rename VFP to S? > --- > gdb/arm-tdep.c | 139 +++++++++++++++++++++++++++++++++++-------------- > gdb/arm-tdep.h | 12 ++++- > 2 files changed, 111 insertions(+), 40 deletions(-) >=20 > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 2a6bfb1b3f7..13bce202585 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -4122,20 +4122,57 @@ arm_neon_quad_type (struct gdbarch *gdbarch) > return tdep->neon_quad_type; > } >=20 > +/* Return true if REGNUM is a Q pseudo register. Return false > + otherwise. > + > + REGNUM is the raw register number and not a pseudo-relative register > + number. */ > + > +static bool > +is_q_pseudo (struct gdbarch *gdbarch, int regnum) > +{ > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + > + /* Q pseudo registers are available for NEON (Q0~Q15). */ > + if (tdep->have_q_pseudos > + && regnum >=3D tdep->q_pseudo_base > + && regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count)) > + return true; > + > + return false; > +} > + > +/* Return true if REGNUM is a VFP pseudo register. Return false > + otherwise. > + > + REGNUM is the raw register number and not a pseudo-relative register > + number. */ > + > +static bool > +is_vfp_pseudo (struct gdbarch *gdbarch, int regnum) > +{ > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + > + if (tdep->have_vfp_pseudos > + && regnum >=3D tdep->vfp_pseudo_base > + && regnum < (tdep->vfp_pseudo_base + tdep->vfp_pseudo_count)) > + return true; > + > + return false; > +} > + > /* Return the GDB type object for the "standard" data type of data in > register N. */ >=20 > static struct type * > arm_register_type (struct gdbarch *gdbarch, int regnum) > { > - int num_regs =3D gdbarch_num_regs (gdbarch); > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); >=20 > - if (gdbarch_tdep (gdbarch)->have_vfp_pseudos > - && regnum >=3D num_regs && regnum < num_regs + 32) > + if (is_vfp_pseudo (gdbarch, regnum)) > return builtin_type (gdbarch)->builtin_float; >=20 > - if (gdbarch_tdep (gdbarch)->have_neon_pseudos > - && regnum >=3D num_regs + 32 && regnum < num_regs + 32 + 16) > + if (is_q_pseudo (gdbarch, regnum)) > return arm_neon_quad_type (gdbarch); >=20 > /* If the target description has register information, we are only > @@ -4147,7 +4184,7 @@ arm_register_type (struct gdbarch *gdbarch, int reg= num) >=20 > if (regnum >=3D ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 > && t->code () =3D=3D TYPE_CODE_FLT > - && gdbarch_tdep (gdbarch)->have_neon) > + && tdep->have_neon) > return arm_neon_double_type (gdbarch); > else > return t; > @@ -4155,7 +4192,7 @@ arm_register_type (struct gdbarch *gdbarch, int reg= num) >=20 > if (regnum >=3D ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) > { > - if (!gdbarch_tdep (gdbarch)->have_fpa_registers) > + if (!tdep->have_fpa_registers) > return builtin_type (gdbarch)->builtin_void; >=20 > return arm_ext_type (gdbarch); > @@ -8551,10 +8588,9 @@ show_disassembly_style_sfunc (struct ui_file *file= , int from_tty, > static const char * > arm_register_name (struct gdbarch *gdbarch, int i) > { > - const int num_regs =3D gdbarch_num_regs (gdbarch); > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); >=20 > - if (gdbarch_tdep (gdbarch)->have_vfp_pseudos > - && i >=3D num_regs && i < num_regs + 32) > + if (is_vfp_pseudo (gdbarch, i)) > { > static const char *const vfp_pseudo_names[] =3D { > "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", > @@ -8563,18 +8599,17 @@ arm_register_name (struct gdbarch *gdbarch, int i= ) > "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", > }; >=20 > - return vfp_pseudo_names[i - num_regs]; > + return vfp_pseudo_names[i - tdep->vfp_pseudo_base]; > } >=20 > - if (gdbarch_tdep (gdbarch)->have_neon_pseudos > - && i >=3D num_regs + 32 && i < num_regs + 32 + 16) > + if (is_q_pseudo (gdbarch, i)) > { > - static const char *const neon_pseudo_names[] =3D { > + static const char *const q_pseudo_names[] =3D { > "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", > "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", > }; >=20 > - return neon_pseudo_names[i - num_regs - 32]; > + return q_pseudo_names[i - tdep->q_pseudo_base]; > } >=20 > if (i >=3D ARRAY_SIZE (arm_register_names)) > @@ -8582,6 +8617,7 @@ arm_register_name (struct gdbarch *gdbarch, int i) > an XML description. */ > return ""; >=20 > + /* Non-pseudo registers. */ > return arm_register_names[i]; > } >=20 > @@ -8719,15 +8755,20 @@ arm_pseudo_read (struct gdbarch *gdbarch, readabl= e_regcache *regcache, > int offset, double_regnum; >=20 > gdb_assert (regnum >=3D num_regs); > - regnum -=3D num_regs; >=20 > - if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >=3D 32 && reg= num < 48) > - /* Quad-precision register. */ > - return arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + > + if (is_q_pseudo (gdbarch, regnum)) > + { > + /* Quad-precision register. */ > + return arm_neon_quad_read (gdbarch, regcache, > + regnum - tdep->q_pseudo_base, buf); > + } > else > { > enum register_status status; >=20 > + regnum -=3D tdep->vfp_pseudo_base; > /* Single-precision register. */ > gdb_assert (regnum < 32); >=20 > @@ -8787,13 +8828,18 @@ arm_pseudo_write (struct gdbarch *gdbarch, struct= regcache *regcache, > int offset, double_regnum; >=20 > gdb_assert (regnum >=3D num_regs); > - regnum -=3D num_regs; >=20 > - if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >=3D 32 && reg= num < 48) > - /* Quad-precision register. */ > - arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + > + if (is_q_pseudo (gdbarch, regnum)) > + { > + /* Quad-precision register. */ > + arm_neon_quad_write (gdbarch, regcache, > + regnum - tdep->q_pseudo_base, buf); > + } > else > { > + regnum -=3D tdep->vfp_pseudo_base; > /* Single-precision register. */ > gdb_assert (regnum < 32); >=20 > @@ -8940,11 +8986,12 @@ arm_gdbarch_init (struct gdbarch_info info, struc= t gdbarch_list *arches) > int i; > bool is_m =3D false; > int vfp_register_count =3D 0; > - bool have_vfp_pseudos =3D false, have_neon_pseudos =3D false; > + bool have_vfp_pseudos =3D false, have_q_pseudos =3D false; > bool have_wmmx_registers =3D false; > bool have_neon =3D false; > bool have_fpa_registers =3D true; > const struct target_desc *tdesc =3D info.target_desc; > + int register_count =3D ARM_NUM_REGS; >=20 > /* If we have an object to base this architecture on, try to determine > its ABI. */ > @@ -9248,7 +9295,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct = gdbarch_list *arches) > their type; otherwise (normally) provide them with > the default type. */ > if (tdesc_unnumbered_register (feature, "q0") =3D=3D 0) > - have_neon_pseudos =3D true; > + have_q_pseudos =3D true; >=20 > have_neon =3D true; > } > @@ -9299,7 +9346,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct = gdbarch_list *arches) > || vfp_register_count =3D=3D 32); > tdep->vfp_register_count =3D vfp_register_count; > tdep->have_vfp_pseudos =3D have_vfp_pseudos; > - tdep->have_neon_pseudos =3D have_neon_pseudos; > + tdep->have_q_pseudos =3D have_q_pseudos; > tdep->have_neon =3D have_neon; >=20 > arm_register_g_packet_guesses (gdbarch); > @@ -9387,7 +9434,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct = gdbarch_list *arches) > /* Information about registers, etc. */ > set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); > set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); > - set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); > + set_gdbarch_num_regs (gdbarch, register_count); > set_gdbarch_register_type (gdbarch, arm_register_type); > set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); >=20 > @@ -9475,21 +9522,29 @@ arm_gdbarch_init (struct gdbarch_info info, struc= t gdbarch_list *arches) > set_tdesc_pseudo_register_name (gdbarch, arm_register_name); >=20 > tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); > + register_count =3D gdbarch_num_regs (gdbarch); >=20 > /* Override tdesc_register_type to adjust the types of VFP > registers for NEON. */ > set_gdbarch_register_type (gdbarch, arm_register_type); > } >=20 > - if (have_vfp_pseudos) > + /* Initialize the pseudo register data. */ > + if (tdep->have_vfp_pseudos) > { > - /* NOTE: These are the only pseudo registers used by > - the ARM target at the moment. If more are added, a > - little more care in numbering will be needed. */ > + /* VFP single precision pseudo registers (S0~S31). */ > + tdep->vfp_pseudo_base =3D register_count; > + tdep->vfp_pseudo_count =3D 32; > + int num_pseudos =3D tdep->vfp_pseudo_count; > + > + if (tdep->have_q_pseudos) > + { > + /* NEON quad precision pseudo registers (Q0~Q15). */ > + tdep->q_pseudo_base =3D register_count + num_pseudos; > + tdep->q_pseudo_count =3D 16; > + num_pseudos +=3D tdep->q_pseudo_count; > + } >=20 > - int num_pseudos =3D 32; > - if (have_neon_pseudos) > - num_pseudos +=3D 16; > set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); > set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); > set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); > @@ -9526,10 +9581,18 @@ arm_dump_tdep (struct gdbarch *gdbarch, struct ui= _file *file) > (int) tdep->have_wmmx_registers); > fprintf_unfiltered (file, _("arm_dump_tdep: vfp_register_count =3D %i\n= "), > (int) tdep->vfp_register_count); > - fprintf_unfiltered (file, _("arm_dump_tdep: have_vfp_pseudos =3D %i\n"= ), > - (int) tdep->have_vfp_pseudos); > - fprintf_unfiltered (file, _("arm_dump_tdep: have_neon_pseudos =3D %i\n= "), > - (int) tdep->have_neon_pseudos); > + fprintf_unfiltered (file, _("arm_dump_tdep: have_vfp_pseudos =3D %s\n"= ), > + tdep->have_vfp_pseudos? "true" : "false"); > + fprintf_unfiltered (file, _("arm_dump_tdep: vfp_pseudo_base =3D %i\n")= , > + (int) tdep->vfp_pseudo_base); > + fprintf_unfiltered (file, _("arm_dump_tdep: vfp_pseudo_count =3D %i\n"= ), > + (int) tdep->vfp_pseudo_count); > + fprintf_unfiltered (file, _("arm_dump_tdep: have_q_pseudos =3D %s\n"), > + tdep->have_q_pseudos? "true" : "false"); > + fprintf_unfiltered (file, _("arm_dump_tdep: q_pseudo_base =3D %i\n"), > + (int) tdep->q_pseudo_base); > + fprintf_unfiltered (file, _("arm_dump_tdep: q_pseudo_count =3D %i\n"), > + (int) tdep->q_pseudo_count); > fprintf_unfiltered (file, _("arm_dump_tdep: have_neon =3D %i\n"), > (int) tdep->have_neon); > fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc =3D 0x%lx\n"), > diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h > index 969e121b55d..614c1a00ab6 100644 > --- a/gdb/arm-tdep.h > +++ b/gdb/arm-tdep.h > @@ -102,9 +102,17 @@ struct gdbarch_tdep > int vfp_register_count; > bool have_vfp_pseudos; /* Are we synthesizing the single precision > VFP registers? */ > - bool have_neon_pseudos; /* Are we synthesizing the quad precision > - NEON registers? Requires > + int vfp_pseudo_base; /* Register number for the first single > + precision VFP pseudo register. */ > + int vfp_pseudo_count; /* Number of single precision VFP pseudo > + registers. */ > + bool have_q_pseudos; /* Are we synthesizing the quad precision > + Q (NEON or MVE) registers? Requires > have_vfp_pseudos. */ > + int q_pseudo_base; /* Register number for the first quad > + precision pseudo register. */ > + int q_pseudo_count; /* Number of quad precision pseudo > + registers. */ > bool have_neon; /* Do we have a NEON unit? */ >=20 > bool is_m; /* Does the target follow the "M" profile. */ > --=20 > 2.25.1 >=20