From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25343 invoked by alias); 7 May 2009 23:13:29 -0000 Received: (qmail 25324 invoked by uid 22791); 7 May 2009 23:13:28 -0000 X-SWARE-Spam-Status: No, hits=-0.1 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_93,MIME_QP_LONG_LINE X-Spam-Check-By: sourceware.org Received: from smtp-out4.blueyonder.co.uk (HELO smtp-out4.blueyonder.co.uk) (195.188.213.7) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 07 May 2009 23:13:20 +0000 Received: from [172.23.170.138] (helo=anti-virus01-09) by smtp-out4.blueyonder.co.uk with smtp (Exim 4.52) id 1M2CmB-0004FZ-G0; Fri, 08 May 2009 00:13:15 +0100 Received: from [77.96.64.254] (helo=bibi) by asmtp-out3.blueyonder.co.uk with esmtp (Exim 4.52) id 1M2CmA-0000BK-F3; Fri, 08 May 2009 00:13:14 +0100 From: "Jon Beniston" To: "'Joel Brobecker'" Cc: References: <266F97CB7CD14C6899877E7D69AA2030@bibi> <20090207041443.GG3676@adacore.com> <26720080D2924381A7049C33A9DEB225@bibi> <20090507164853.GD659@adacore.com> Subject: RE: [PATCH] Add support for the Lattice Mico32 (LM32) architecture Date: Thu, 07 May 2009 23:13:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_00B1_01C9CF71.C4976500" In-Reply-To: <20090507164853.GD659@adacore.com> Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2009-05/txt/msg00167.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_00B1_01C9CF71.C4976500 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-length: 869 Hi Joel, Thanks for the second review. > You don't need the func_end variable, here, as you can just pass NULL instead. Ok, I've updated that. > That being said, I'm afraid that you won't be > able to commit this patch until the sim > counterpart is approved. This is due to the > two dependencies (one in configure.tgt, and one > in lm32-tdep.c) that you have. Have you > heard from the sim maintainers? I haven't heard anything yet. Cheers, Jon ChangeLog gdb 2009-05-08 Jon Beniston * MAINTAINERS: Add lm32 target. * Makefile.in: Add lm32 dependencies. * NEWS: Indicate lm32 is a new target. * configure.tgt: Add lm32 targets. * lm32-tdep.c: New file. gdb/testsuite 2009-05-08 Jon Beniston * gdb.asm/asm-source.exp: Add lm32 target. ------=_NextPart_000_00B1_01C9CF71.C4976500 Content-Type: application/octet-stream; name="lm32.patch.2" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="lm32.patch.2" Content-length: 25648 Index: gdb/MAINTAINERS=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/MAINTAINERS,v=0A= retrieving revision 1.413=0A= diff -u -p -r1.413 MAINTAINERS=0A= --- gdb/MAINTAINERS 27 Feb 2009 15:03:47 -0000 1.413=0A= +++ gdb/MAINTAINERS 15 Apr 2009 17:21:19 -0000=0A= @@ -270,6 +270,8 @@ the native maintainer when resolving ABI=0A= ia64 --target=3Dia64-linux-gnu ,-Werror=0A= (--target=3Dia64-elf broken)=0A= =20=0A= + lm32 --target=3Dlm32-elf ,-Werror=0A= +=0A= m32c --target=3Dm32c-elf ,-Werror=0A= Jim Blandy, jimb@codesourcery.com=0A= =20=0A= Index: gdb/Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/Makefile.in,v=0A= retrieving revision 1.1076=0A= diff -u -p -r1.1076 Makefile.in=0A= --- gdb/Makefile.in 30 Mar 2009 19:54:19 -0000 1.1076=0A= +++ gdb/Makefile.in 15 Apr 2009 17:21:19 -0000=0A= @@ -485,6 +485,7 @@ ALL_TARGET_OBS =3D \=0A= i386-dicos-tdep.o \=0A= iq2000-tdep.o \=0A= linux-tdep.o \=0A= + lm32-tdep.o \=0A= m32c-tdep.o \=0A= m32r-linux-tdep.o m32r-tdep.o \=0A= m68hc11-tdep.o \=0A= @@ -1308,6 +1309,7 @@ ALLDEPFILES =3D \=0A= libunwind-frame.c \=0A= linux-fork.c \=0A= linux-tdep.c \=0A= + lm32-tdep.c \=0A= m68hc11-tdep.c \=0A= m32r-tdep.c \=0A= m32r-linux-nat.c m32r-linux-tdep.c \=0A= Index: gdb/NEWS=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/NEWS,v=0A= retrieving revision 1.305=0A= diff -u -p -r1.305 NEWS=0A= --- gdb/NEWS 31 Mar 2009 20:21:06 -0000 1.305=0A= +++ gdb/NEWS 15 Apr 2009 17:21:21 -0000=0A= @@ -234,6 +234,7 @@ x86_64 MinGW x86_64-*-mingw*=0A= =20=0A= * New targets=0A= =20=0A= +Lattice Mico32 lm32-*=0A= x86 DICOS i[34567]86-*-dicos*=0A= x86_64 DICOS x86_64-*-dicos*=0A= =20=0A= Index: gdb/configure.tgt=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/configure.tgt,v=0A= retrieving revision 1.213=0A= diff -u -p -r1.213 configure.tgt=0A= --- gdb/configure.tgt 16 Mar 2009 15:04:14 -0000 1.213=0A= +++ gdb/configure.tgt 15 Apr 2009 17:21:22 -0000=0A= @@ -231,6 +231,11 @@ iq2000-*-*)=0A= gdb_sim=3D../sim/iq2000/libsim.a=0A= ;;=0A= =20=0A= +lm32-*-*)=09=09=0A= + gdb_target_obs=3D"lm32-tdep.o"=20=0A= + gdb_sim=3D../sim/lm32/libsim.a=0A= + ;;=0A= +=0A= m32c-*-*)=0A= # Target: Renesas M32C family=0A= gdb_target_obs=3D"m32c-tdep.o prologue-value.o"=0A= Index: gdb/lm32-tdep.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: gdb/lm32-tdep.c=0A= diff -N gdb/lm32-tdep.c=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ gdb/lm32-tdep.c 15 Apr 2009 17:21:22 -0000=0A= @@ -0,0 +1,585 @@=0A= +/* Target-dependent code for Lattice Mico32 processor, for GDB.=0A= + Contributed by Jon Beniston =0A= +=0A= + Copyright (C) 2009 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=0A= +#include "defs.h"=0A= +#include "frame.h"=0A= +#include "frame-unwind.h"=0A= +#include "frame-base.h"=0A= +#include "inferior.h"=0A= +#include "dis-asm.h"=0A= +#include "symfile.h"=0A= +#include "remote.h"=0A= +#include "gdbcore.h"=0A= +#include "gdb/sim-lm32.h"=0A= +#include "gdb/callback.h"=0A= +#include "gdb/remote-sim.h"=0A= +#include "sim-regno.h"=0A= +#include "arch-utils.h"=0A= +#include "regcache.h"=0A= +#include "trad-frame.h"=0A= +#include "reggroups.h"=0A= +#include "opcodes/lm32-desc.h"=0A= +=0A= +#include "gdb_string.h"=0A= +=0A= +/* Macros to extract fields from an instruction. */=0A= +#define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)=0A= +#define LM32_REG0(insn) ((insn >> 21) & 0x1f)=0A= +#define LM32_REG1(insn) ((insn >> 16) & 0x1f)=0A= +#define LM32_REG2(insn) ((insn >> 11) & 0x1f)=0A= +#define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)=0A= +=0A= +struct gdbarch_tdep=0A= +{=0A= + /* gdbarch target dependent data here. Currently unused for LM32. */=0A= +};=0A= +=0A= +struct lm32_frame_cache=0A= +{=0A= + /* The frame's base. Used when constructing a frame ID. */=0A= + CORE_ADDR base;=0A= + CORE_ADDR pc;=0A= + /* Size of frame. */=0A= + int size;=0A= + /* Table indicating the location of each and every register. */=0A= + struct trad_frame_saved_reg *saved_regs;=0A= +};=0A= +=0A= +/* Add the available register groups. */=0A= +=0A= +static void=0A= +lm32_add_reggroups (struct gdbarch *gdbarch)=0A= +{=0A= + reggroup_add (gdbarch, general_reggroup);=0A= + reggroup_add (gdbarch, all_reggroup);=0A= + reggroup_add (gdbarch, system_reggroup);=0A= +}=0A= +=0A= +/* Return whether a given register is in a given group. */=0A= +=0A= +static int=0A= +lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,=0A= + struct reggroup *group)=0A= +{=0A= + if (group =3D=3D general_reggroup)=0A= + return ((regnum >=3D SIM_LM32_R0_REGNUM) && (regnum <=3D SIM_LM32_RA_R= EGNUM))=0A= + || (regnum =3D=3D SIM_LM32_PC_REGNUM);=0A= + else if (group =3D=3D system_reggroup)=0A= + return ((regnum >=3D SIM_LM32_EA_REGNUM) && (regnum <=3D SIM_LM32_BA_R= EGNUM))=0A= + || ((regnum >=3D SIM_LM32_EID_REGNUM) && (regnum <=3D SIM_LM32_IP_RE= GNUM));=0A= + return default_register_reggroup_p (gdbarch, regnum, group);=0A= +}=0A= +=0A= +/* Return a name that corresponds to the given register number. */=0A= +=0A= +static const char *=0A= +lm32_register_name (struct gdbarch *gdbarch, int reg_nr)=0A= +{=0A= + static char *register_names[] =3D {=0A= + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",=0A= + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",=0A= + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",=0A= + "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",=0A= + "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"=0A= + };=0A= +=0A= + if ((reg_nr < 0) || (reg_nr >=3D ARRAY_SIZE (register_names)))=0A= + return NULL;=0A= + else=0A= + return register_names[reg_nr];=0A= +}=0A= +=0A= +/* Return type of register. */=0A= +=0A= +static struct type *=0A= +lm32_register_type (struct gdbarch *gdbarch, int reg_nr)=0A= +{=0A= + return builtin_type_int32;=0A= +}=0A= +=0A= +/* Return non-zero if a register can't be written. */=0A= +=0A= +static int=0A= +lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)=0A= +{=0A= + return (regno =3D=3D SIM_LM32_R0_REGNUM) || (regno =3D=3D SIM_LM32_EID_R= EGNUM);=0A= +}=0A= +=0A= +/* Analyze a function's prologue. */=0A= +=0A= +static CORE_ADDR=0A= +lm32_analyze_prologue (CORE_ADDR pc, CORE_ADDR limit,=0A= + struct lm32_frame_cache *info)=0A= +{=0A= + unsigned long instruction;=0A= +=0A= + /* Keep reading though instructions, until we come across an instruction= =20=0A= + that isn't likely to be part of the prologue. */=0A= + info->size =3D 0;=0A= + for (; pc < limit; pc +=3D 4)=0A= + {=0A= +=0A= + /* Read an instruction. */=0A= + instruction =3D read_memory_integer (pc, 4);=0A= +=0A= + if ((LM32_OPCODE (instruction) =3D=3D OP_SW)=0A= + && (LM32_REG0 (instruction) =3D=3D SIM_LM32_SP_REGNUM))=0A= + {=0A= + /* Any stack displaced store is likely part of the prologue.=20=20=0A= + Record that the register is being saved, and the offset=20=0A= + into the stack. */=0A= + info->saved_regs[LM32_REG1 (instruction)].addr =3D=0A= + LM32_IMM16 (instruction);=0A= + }=0A= + else if ((LM32_OPCODE (instruction) =3D=3D OP_ADDI)=0A= + && (LM32_REG1 (instruction) =3D=3D SIM_LM32_SP_REGNUM))=0A= + {=0A= + /* An add to the SP is likely to be part of the prologue.=20=20=0A= + Adjust stack size by whatever the instruction adds to the sp. */=0A= + info->size -=3D LM32_IMM16 (instruction);=0A= + }=0A= + else if ( /* add fp,fp,sp */=0A= + ((LM32_OPCODE (instruction) =3D=3D OP_ADD)=0A= + && (LM32_REG2 (instruction) =3D=3D SIM_LM32_FP_REGNUM)=0A= + && (LM32_REG0 (instruction) =3D=3D SIM_LM32_FP_REGNUM)=0A= + && (LM32_REG1 (instruction) =3D=3D SIM_LM32_SP_REGNUM))=0A= + /* mv fp,imm */=0A= + || ((LM32_OPCODE (instruction) =3D=3D OP_ADDI)=0A= + && (LM32_REG1 (instruction) =3D=3D SIM_LM32_FP_REGNUM)=0A= + && (LM32_REG0 (instruction) =3D=3D SIM_LM32_R0_REGNUM)))=0A= + {=0A= + /* Likely to be in the prologue for functions that require=20=0A= + a frame pointer. */=0A= + }=0A= + else=0A= + {=0A= + /* Any other instruction is likely not to be part of the prologue. */= =0A= + break;=0A= + }=0A= + }=0A= +=0A= + return pc;=0A= +}=0A= +=0A= +/* Return PC of first non prologue instruction, for the function at the=20= =0A= + specified address. */=0A= +=0A= +static CORE_ADDR=0A= +lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= +{=0A= + CORE_ADDR func_addr, limit_pc;=0A= + struct symtab_and_line sal;=0A= + struct lm32_frame_cache frame_info;=0A= + struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];=0A= +=0A= + /* See if we can determine the end of the prologue via the symbol table.= =0A= + If so, then return either PC, or the PC after the prologue, whichever= =0A= + is greater. */=0A= + if (find_pc_partial_function (pc, NULL, &func_addr, NULL))=0A= + {=0A= + CORE_ADDR post_prologue_pc =3D skip_prologue_using_sal (func_addr);= =0A= + if (post_prologue_pc !=3D 0)=0A= + return max (pc, post_prologue_pc);=0A= + }=0A= +=0A= + /* Can't determine prologue from the symbol table, need to examine=0A= + instructions. */=0A= +=0A= + /* Find an upper limit on the function prologue using the debug=0A= + information. If the debug information could not be used to provide= =0A= + that bound, then use an arbitrary large number as the upper bound. *= /=0A= + limit_pc =3D skip_prologue_using_sal (pc);=0A= + if (limit_pc =3D=3D 0)=0A= + limit_pc =3D pc + 100; /* Magic. */=0A= +=0A= + frame_info.saved_regs =3D saved_regs;=0A= + return lm32_analyze_prologue (pc, limit_pc, &frame_info);=0A= +}=0A= +=0A= +/* Create a breakpoint instruction. */=0A= +=0A= +static const gdb_byte *=0A= +lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,=0A= + int *lenptr)=0A= +{=0A= + static const gdb_byte breakpoint[4] =3D { OP_RAISE << 2, 0, 0, 2 };=0A= +=0A= + *lenptr =3D sizeof (breakpoint);=0A= + return breakpoint;=0A= +}=0A= +=0A= +/* Setup registers and stack for faking a call to a function in the=20=0A= + inferior. */=0A= +=0A= +static CORE_ADDR=0A= +lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,=0A= + struct regcache *regcache, CORE_ADDR bp_addr,=0A= + int nargs, struct value **args, CORE_ADDR sp,=0A= + int struct_return, CORE_ADDR struct_addr)=0A= +{=0A= + int first_arg_reg =3D SIM_LM32_R1_REGNUM;=0A= + int num_arg_regs =3D 8;=0A= + int i;=0A= +=0A= + /* Set the return address. */=0A= + regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);=0A= +=0A= + /* If we're returning a large struct, a pointer to the address to=0A= + store it at is passed as a first hidden parameter. */=0A= + if (struct_return)=0A= + {=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr= );=0A= + first_arg_reg++;=0A= + num_arg_regs--;=0A= + sp -=3D 4;=0A= + }=0A= +=0A= + /* Setup parameters. */=0A= + for (i =3D 0; i < nargs; i++)=0A= + {=0A= + struct value *arg =3D args[i];=0A= + struct type *arg_type =3D check_typedef (value_type (arg));=0A= + gdb_byte *contents;=0A= + int len;=0A= + int j;=0A= + int reg;=0A= + ULONGEST val;=0A= +=0A= + /* Promote small integer types to int. */=0A= + switch (TYPE_CODE (arg_type))=0A= + {=0A= + case TYPE_CODE_INT:=0A= + case TYPE_CODE_BOOL:=0A= + case TYPE_CODE_CHAR:=0A= + case TYPE_CODE_RANGE:=0A= + case TYPE_CODE_ENUM:=0A= + if (TYPE_LENGTH (arg_type) < 4)=0A= + {=0A= + arg_type =3D builtin_type_int32;=0A= + arg =3D value_cast (arg_type, arg);=0A= + }=0A= + break;=0A= + }=0A= +=0A= + /* FIXME: Handle structures. */=0A= +=0A= + contents =3D (gdb_byte *) value_contents (arg);=0A= + len =3D TYPE_LENGTH (arg_type);=0A= + val =3D extract_unsigned_integer (contents, len);=0A= +=0A= + /* First num_arg_regs parameters are passed by registers,=20=0A= + and the rest are passed on the stack. */=0A= + if (i < num_arg_regs)=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);=0A= + else=0A= + {=0A= + write_memory (sp, (void *) &val, len);=0A= + sp -=3D 4;=0A= + }=0A= + }=0A= +=0A= + /* Update stack pointer. */=0A= + regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);=0A= +=0A= + /* Return adjusted stack pointer. */=0A= + return sp;=0A= +}=0A= +=0A= +/* Extract return value after calling a function in the inferior. */=0A= +=0A= +static void=0A= +lm32_extract_return_value (struct type *type, struct regcache *regcache,= =0A= + gdb_byte *valbuf)=0A= +{=0A= + int offset;=0A= + ULONGEST l;=0A= + CORE_ADDR return_buffer;=0A= +=0A= + if (TYPE_CODE (type) !=3D TYPE_CODE_STRUCT=0A= + && TYPE_CODE (type) !=3D TYPE_CODE_UNION=0A= + && TYPE_CODE (type) !=3D TYPE_CODE_ARRAY && TYPE_LENGTH (type) <=3D = 4)=0A= + {=0A= + /* Return value is returned in a single register. */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);=0A= + store_unsigned_integer (valbuf, TYPE_LENGTH (type), l);=0A= + }=0A= + else if ((TYPE_CODE (type) =3D=3D TYPE_CODE_INT) && (TYPE_LENGTH (type) = =3D=3D 8))=0A= + {=0A= + /* 64-bit values are returned in a register pair. */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);=0A= + memcpy (valbuf, &l, 4);=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);=0A= + memcpy (valbuf + 4, &l, 4);=0A= + }=0A= + else=0A= + {=0A= + /* Aggregate types greater than a single register are returned in me= mory.=20=0A= + FIXME: Unless they are only 2 regs?. */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);=0A= + return_buffer =3D l;=0A= + read_memory (return_buffer, valbuf, TYPE_LENGTH (type));=0A= + }=0A= +}=0A= +=0A= +/* Write into appropriate registers a function return value of type=0A= + TYPE, given in virtual format. */=0A= +static void=0A= +lm32_store_return_value (struct type *type, struct regcache *regcache,=0A= + const gdb_byte *valbuf)=0A= +{=0A= + ULONGEST val;=0A= + int len =3D TYPE_LENGTH (type);=0A= +=0A= + if (len <=3D 4)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, len);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);= =0A= + }=0A= + else if (len <=3D 8)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, 4);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);= =0A= + val =3D extract_unsigned_integer (valbuf + 4, len - 4);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);= =0A= + }=0A= + else=0A= + error (_("lm32_store_return_value: type length too large."));=0A= +}=0A= +=0A= +/* Determine whether a functions return value is in a register or memory. = */=0A= +static enum return_value_convention=0A= +lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,=0A= + struct type *valtype, struct regcache *regcache,=0A= + gdb_byte *readbuf, const gdb_byte *writebuf)=0A= +{=0A= + enum type_code code =3D TYPE_CODE (valtype);=0A= +=0A= + if (code =3D=3D TYPE_CODE_STRUCT=0A= + || code =3D=3D TYPE_CODE_UNION=0A= + || code =3D=3D TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)=0A= + return RETURN_VALUE_STRUCT_CONVENTION;=0A= +=0A= + if (readbuf)=0A= + lm32_extract_return_value (valtype, regcache, readbuf);=0A= + if (writebuf)=0A= + lm32_store_return_value (valtype, regcache, writebuf);=0A= +=0A= + return RETURN_VALUE_REGISTER_CONVENTION;=0A= +}=0A= +=0A= +static CORE_ADDR=0A= +lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)=0A= +{=0A= + return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);= =0A= +}=0A= +=0A= +static CORE_ADDR=0A= +lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)=0A= +{=0A= + return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);= =0A= +}=0A= +=0A= +static struct frame_id=0A= +lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)=0A= +{=0A= + CORE_ADDR sp =3D get_frame_register_unsigned (this_frame, SIM_LM32_SP_RE= GNUM);=0A= +=0A= + return frame_id_build (sp, get_frame_pc (this_frame));=0A= +}=0A= +=0A= +/* Put here the code to store, into fi->saved_regs, the addresses of=0A= + the saved registers of frame described by FRAME_INFO. This=0A= + includes special registers such as pc and fp saved in special ways=0A= + in the stack frame. sp is even more special: the address we return=0A= + for it IS the sp for the next frame. */=0A= +=0A= +static struct lm32_frame_cache *=0A= +lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cach= e)=0A= +{=0A= + CORE_ADDR prologue_pc;=0A= + CORE_ADDR current_pc;=0A= + ULONGEST prev_sp;=0A= + ULONGEST this_base;=0A= + struct lm32_frame_cache *info;=0A= + int prefixed;=0A= + unsigned long instruction;=0A= + int op;=0A= + int offsets[32];=0A= + int i;=0A= + long immediate;=0A= +=0A= + if ((*this_prologue_cache))=0A= + return (*this_prologue_cache);=0A= +=0A= + info =3D FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);=0A= + (*this_prologue_cache) =3D info;=0A= + info->saved_regs =3D trad_frame_alloc_saved_regs (this_frame);=0A= +=0A= + info->pc =3D get_frame_func (this_frame);=0A= + current_pc =3D get_frame_pc (this_frame);=0A= + lm32_analyze_prologue (info->pc, current_pc, info);=0A= +=0A= + /* Compute the frame's base, and the previous frame's SP. */=0A= + this_base =3D get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNU= M);=0A= + prev_sp =3D this_base + info->size;=0A= + info->base =3D this_base;=0A= +=0A= + /* Convert callee save offsets into addresses. */=0A= + for (i =3D 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i+= +)=0A= + {=0A= + if (trad_frame_addr_p (info->saved_regs, i))=0A= + info->saved_regs[i].addr =3D this_base + info->saved_regs[i].addr;=0A= + }=0A= +=0A= + /* The call instruction moves the caller's PC in the callee's RA registe= r.=0A= + Since this is an unwind, do the reverse. Copy the location of RA reg= ister=0A= + into PC (the address / regnum) so that a request for PC will be=0A= + converted into a request for the RA register. */=0A= + info->saved_regs[SIM_LM32_PC_REGNUM] =3D info->saved_regs[SIM_LM32_RA_RE= GNUM];=0A= +=0A= + /* The previous frame's SP needed to be computed. Save the computed val= ue. */=0A= + trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);=0A= +=0A= + return info;=0A= +}=0A= +=0A= +static void=0A= +lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,=0A= + struct frame_id *this_id)=0A= +{=0A= + struct lm32_frame_cache *cache =3D lm32_frame_cache (this_frame, this_ca= che);=0A= +=0A= + /* This marks the outermost frame. */=0A= + if (cache->base =3D=3D 0)=0A= + return;=0A= +=0A= + (*this_id) =3D frame_id_build (cache->base, cache->pc);=0A= +}=0A= +=0A= +static struct value *=0A= +lm32_frame_prev_register (struct frame_info *this_frame,=0A= + void **this_prologue_cache, int regnum)=0A= +{=0A= + struct lm32_frame_cache *info;=0A= +=0A= + info =3D lm32_frame_cache (this_frame, this_prologue_cache);=0A= + return trad_frame_get_prev_register (this_frame, info->saved_regs, regnu= m);=0A= +}=0A= +=0A= +static const struct frame_unwind lm32_frame_unwind =3D {=0A= + NORMAL_FRAME,=0A= + lm32_frame_this_id,=0A= + lm32_frame_prev_register,=0A= + NULL,=0A= + default_frame_sniffer=0A= +};=0A= +=0A= +static CORE_ADDR=0A= +lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)= =0A= +{=0A= + struct lm32_frame_cache *info =3D lm32_frame_cache (this_frame, this_cac= he);=0A= +=0A= + return info->base;=0A= +}=0A= +=0A= +static const struct frame_base lm32_frame_base =3D {=0A= + &lm32_frame_unwind,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address=0A= +};=0A= +=0A= +static CORE_ADDR=0A= +lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)=0A= +{=0A= + /* Align to the size of an instruction (so that they can safely be=0A= + pushed onto the stack. */=0A= + return sp & ~3;=0A= +}=0A= +=0A= +static struct gdbarch *=0A= +lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)= =0A= +{=0A= + struct gdbarch *gdbarch;=0A= + struct gdbarch_tdep *tdep;=0A= +=0A= + /* If there is already a candidate, use it. */=0A= + arches =3D gdbarch_list_lookup_by_info (arches, &info);=0A= + if (arches !=3D NULL)=0A= + return arches->gdbarch;=0A= +=0A= + /* None found, create a new architecture from the information provided. = */=0A= + tdep =3D XMALLOC (struct gdbarch_tdep);=0A= + gdbarch =3D gdbarch_alloc (&info, tdep);=0A= +=0A= + /* Type sizes. */=0A= + set_gdbarch_short_bit (gdbarch, 16);=0A= + set_gdbarch_int_bit (gdbarch, 32);=0A= + set_gdbarch_long_bit (gdbarch, 32);=0A= + set_gdbarch_long_long_bit (gdbarch, 64);=0A= + set_gdbarch_float_bit (gdbarch, 32);=0A= + set_gdbarch_double_bit (gdbarch, 64);=0A= + set_gdbarch_long_double_bit (gdbarch, 64);=0A= + set_gdbarch_ptr_bit (gdbarch, 32);=0A= +=0A= + /* Register info. */=0A= + set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);=0A= + set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);=0A= + set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);=0A= + set_gdbarch_register_name (gdbarch, lm32_register_name);=0A= + set_gdbarch_register_type (gdbarch, lm32_register_type);=0A= + set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);= =0A= +=0A= + /* Frame info. */=0A= + set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);=0A= + set_gdbarch_inner_than (gdbarch, core_addr_lessthan);=0A= + set_gdbarch_decr_pc_after_break (gdbarch, 0);=0A= + set_gdbarch_frame_args_skip (gdbarch, 0);=0A= +=0A= + /* Frame unwinding. */=0A= + set_gdbarch_frame_align (gdbarch, lm32_frame_align);=0A= + frame_base_set_default (gdbarch, &lm32_frame_base);=0A= + set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);=0A= + set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);=0A= + set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);=0A= + frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);=0A= +=0A= + /* Breakpoints. */=0A= + set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);=0A= + set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);=0A= +=0A= + /* Calling functions in the inferior. */=0A= + set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);=0A= + set_gdbarch_return_value (gdbarch, lm32_return_value);=0A= +=0A= + /* Instruction disassembler. */=0A= + set_gdbarch_print_insn (gdbarch, print_insn_lm32);=0A= +=0A= + lm32_add_reggroups (gdbarch);=0A= + set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);=0A= +=0A= + return gdbarch;=0A= +}=0A= +=0A= +void=0A= +_initialize_lm32_tdep (void)=0A= +{=0A= + register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);=0A= +}=0A= Index: gdb/testsuite/gdb.asm/asm-source.exp=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/testsuite/gdb.asm/asm-source.exp,v=0A= retrieving revision 1.73=0A= diff -u -p -r1.73 asm-source.exp=0A= --- gdb/testsuite/gdb.asm/asm-source.exp 3 Jan 2009 05:58:03 -0000 1.73=0A= +++ gdb/testsuite/gdb.asm/asm-source.exp 15 Apr 2009 17:21:23 -0000=0A= @@ -64,6 +64,9 @@ switch -glob -- [istarget] {=0A= "i\[3456\]86-*-*" {=0A= set asm-arch i386=0A= }=0A= + "lm32-*" {=0A= + set asm-arch lm32=0A= + }=0A= "m32r*-linux*" {=0A= set asm-arch m32r-linux=0A= }=0A= ------=_NextPart_000_00B1_01C9CF71.C4976500--