From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 120492 invoked by alias); 19 Apr 2016 14:23:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 120476 invoked by uid 89); 19 Apr 2016 14:23:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=Tuesday, tuesday, road, commercial X-HELO: mga02.intel.com Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 19 Apr 2016 14:22:51 +0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP; 19 Apr 2016 07:13:54 -0700 X-ExtLoop1: 1 Received: from irsmsx151.ger.corp.intel.com ([163.33.192.59]) by fmsmga004.fm.intel.com with ESMTP; 19 Apr 2016 07:13:53 -0700 Received: from irsmsx156.ger.corp.intel.com (10.108.20.68) by IRSMSX151.ger.corp.intel.com (163.33.192.59) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 19 Apr 2016 15:13:21 +0100 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.87]) by IRSMSX156.ger.corp.intel.com ([169.254.3.32]) with mapi id 14.03.0248.002; Tue, 19 Apr 2016 15:13:21 +0100 From: "Tedeschi, Walfred" To: Richard Henderson , "gdb-patches@gcc.gnu.org" Subject: RE: [PATCH 0/3] Support for x86 segments as address classes Date: Tue, 19 Apr 2016 14:23:00 -0000 Message-ID: References: <1446558190-13482-1-git-send-email-rth@redhat.com> In-Reply-To: <1446558190-13482-1-git-send-email-rth@redhat.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-04/txt/msg00444.txt.bz2 -----Original Message----- From: gdb-patches-owner@sourceware.org [mailto:gdb-patches-owner@sourceware= .org] On Behalf Of Richard Henderson Sent: Tuesday, November 03, 2015 2:43 PM To: gdb-patches@gcc.gnu.org Subject: [PATCH 0/3] Support for x86 segments as address classes The following gets 90% of the way there, but I'm stuck -- address_to_pointe= r and pointer_to_address do not appear to have access to a regcache. And n= ot just in the one level of the caller, but significantly farther back in t= he call stack too. Which begs the question of whether I've simply missed something in how to g= et hold of the current regcache? r~ Richard Henderson (3): Add amd64 registers fs_base and gs_base Use register cache for x86_64 ps_get_thread_area Segment support for x86_64, part 1 gdb/amd64-linux-nat.c | 107 ++++++++-------- gdb/amd64-linux-tdep.c | 5 + gdb/amd64-linux-tdep.h | 2 +- gdb/amd64-tdep.c | 68 ++++++++++ gdb/amd64-tdep.h | 6 +- gdb/features/i386/64bit-seg.xml | 12 ++ gdb/features/i386/amd64-avx-linux.c | 36 +++--- gdb/features/i386/amd64-avx-linux.xml | 1 + gdb/features/i386/amd64-avx512-linux.c | 192 +++++++++++++++----------= ---- gdb/features/i386/amd64-avx512-linux.xml | 1 + gdb/features/i386/amd64-linux.c | 4 + gdb/features/i386/amd64-linux.xml | 1 + gdb/features/i386/amd64-mpx-linux.c | 48 ++++---- gdb/features/i386/amd64-mpx-linux.xml | 1 + gdb/features/i386/x32-avx-linux.c | 36 +++--- gdb/features/i386/x32-avx-linux.xml | 1 + gdb/features/i386/x32-avx512-linux.c | 192 +++++++++++++++----------= ---- gdb/features/i386/x32-avx512-linux.xml | 1 + gdb/features/i386/x32-linux.c | 4 + gdb/features/i386/x32-linux.xml | 1 + gdb/regformats/i386/amd64-avx-linux.dat | 2 + gdb/regformats/i386/amd64-avx512-linux.dat | 2 + gdb/regformats/i386/amd64-linux.dat | 2 + gdb/regformats/i386/amd64-mpx-linux.dat | 2 + gdb/regformats/i386/x32-avx-linux.dat | 2 + gdb/regformats/i386/x32-avx512-linux.dat | 2 + gdb/regformats/i386/x32-linux.dat | 2 + 27 files changed, 438 insertions(+), 295 deletions(-) create mode 100644 = gdb/features/i386/64bit-seg.xml -- 2.4.3 Richard, I was about to prepare also a patch about the same topic. Intention is to make fs_base and gs_base available for the user. Have you gave up this patch, or have you found some road blocker? Thanks and regard, -Fred Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928